Analog Devices ADAV4601, Документ по проектированию системы

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ADAV4601 System Design Document Confidential Information
Rev.1 August 2009 Analog Devices Page 20
PWM1A
PWM1B
PWM Ready
365ms 206us
Differential PWM
in phase
Differential PWM
out of phase –
valid audio
PWM Ready Early
PWM Enable
Sequences
PWM1A
PWM1B
PWM Ready
365ms 206us
Differential PWM
in phase
Differential PWM
out of phase –
valid audio
PWM Ready Early
PWM Enable
Sequences
Figure 12: PWM Ready Signal
34 001E 818A
This register setting is used to enable the PWM low signal clamping, if the input to the PWM block from the audio
processor goes below the low-level threshold also set by this write, the output of the PWM generator is muted, i.e.
PWM generators produce a 50/50 duty cycle.
34 008F 000F
This register sets the PWM clamp release time. This controls the number of consecutive samples that the PWM will
stay muted after the signal that is inputted to the PWM block was outside the threshold limit set by the previous
register write. This ensures that low level spurious responses are kept muted until valid audio is ready to be
outputted. This register write sets the clamp time to be 11 samples. This means that once the input goes above the
threshold set by the previous register write, no sound will appear on the output of the PWM generator for at least
11 samples.
34 0126 0150
This register write is used to initialize the SRC delay buffer in the default audio flow. Once the SRC starts outputting
valid audio, this is stored in the audio flow buffer. Once the un-mute signal for the audio flow has been set, the
buffer in the audio flow starts outputting valid audio. The one requirement for this is to ensure that the SRC un-
mute signal delay (set by register 0082 and 0087) is marginally longer than the audio flow SRC buffer delay (set by
register 0126). Refer to Figure 11 for more details on setting the SRC delay buffer.
34 000A 5F81
This register is the miscellaneous control register. By setting this register to this value, the four PWM channels are
enabled and also the PWM enable and disable sequences. These are specially constructed patterns which are used
to bring the PWM channels from a zero condition to a 50/50 duty cycle. Refer to Figure 12 for more details on the
PWM enable sequences. This register is also used to enable the MCLK_OUT function; this means the part can output
a clock on the MCLK_OUT pin which can be used to clock another device. Should this function be required this bit
must be set.
Note: This register was written to previously to enable the PLL. Therefore when writing to this register care must be
taken not to disable the PLL as this will affect the operation of the device.
34 0100 7077
34 0101 7777
These registers control the input multiplexers in the default audio flow. These writes send the data that is on the
SRC1 channel to all the available outputs: Tweeter, Woofer, AUXDAC1, AUXDAC3, SPDIF and SDO0. Once these
registers have been set the part must then be un-muted.
34 0121 00FF
This register write, un-mutes the ADAV4601. If the there is data on the SRC1 channel this should now be available
on all outputs.