ADAV4601 System Design Document
Confidential Information
Rev.1 August 2009
Analog Devices
Page 19
Note:
This is the final register write, which is used to power up the DAC. At this point in the power up sequence, the
DACs are fully powered up and ready to be used.
34 0081 0202
34 0086 0202
Once the SRC detects invalid data, the outputs of the SRC are slewed to a muted state. However in the default audio
flow there is a slew which controls the mute and un-mute function on the output from the SRC. As it would be
undesirable to have two slews controlling the same thing, these two register writes disable the internal SRC mute
slew so that the only one controlling that mute and un-mute function on the SRC output is that which is in the
default audio flow.
34 0082 1843
34 0087 1843
These register writes set the delay for the SRC un-mute signal from both the SRC1 and SRC2 to 7.1ms from when the
output of the SRC is un-muted. Refer to Figure 11 for more details regarding this un-muting sequence.
Valid Data
SRC
Audio Flow
SRC Buffer/Delay
SRC Mute
A
B
(B) Output from SRC
Valid Data
(A) Input to SRC
(C) Output from Buffer
C
(D) SRC Un-mute Signal
D
(E) SRC Input to Flow
Valid Data
E
Valid Data
SRC Un-mute Signal Delay, set
by register 0x0082 and 0x0087
Buffer Delay, set by register
0x0126 in the default flow.
Valid Data
SRC
Audio Flow
SRC Buffer/Delay
SRC Mute
A
B
(B) Output from SRC
Valid Data
(A) Input to SRC
(C) Output from Buffer
C
(D) SRC Un-mute Signal
D
(E) SRC Input to Flow
Valid Data
E
Valid Data
SRC Un-mute Signal Delay, set
by register 0x0082 and 0x0087
Buffer Delay, set by register
0x0126 in the default flow.
SRC
Audio Flow
SRC Buffer/Delay
SRC Mute
A
B
(B) Output from SRC
Valid Data
(A) Input to SRC
(C) Output from Buffer
C
(D) SRC Un-mute Signal
D
(E) SRC Input to Flow
Valid Data
E
Valid Data
SRC Un-mute Signal Delay, set
by register 0x0082 and 0x0087
Buffer Delay, set by register
0x0126 in the default flow.
Figure 11: SRC Unmute Sequence
Once there is valid audio in the SRC, the SRC un-mutes immediately, however there is a buffer in the default audio
flow, which stores samples from the output of the SRC. This buffer must be full of valid data before it is in turn un-
muted and data sent to the audio flow. Therefore, the un-mute signal from the SRC is delayed by a time, which is
just marginally longer than that of the time taken to fill the audio flow buffer. If full of valid data, this is then un-
muted and data is sent to the audio flow.
34 001F D890
This register is the PWM control register 2. By setting this register to this value, the PWM outputs are re-synced at
the output pads by a clock from the digital core of the ADAV46xx. By default all 4 PWM outputs from the ADAV4601
are phase shifted by 45°. By resyncing them at the output, they are all re-aligned. This register write enables the
PWM ready early signal. This PWM ready output from the ADAV4601 can be used to indicate to an external
microcontroller that an external power stage can be un-muted. Refer to Figure 12 for more information on how the
PWM ready signal relates to the PWM outputs.
Содержание ADAV4601
Страница 107: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 107 APPENDIX D SCHEMATICS...
Страница 108: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 108...
Страница 109: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 109...
Страница 110: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 110...
Страница 111: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 111...
Страница 112: ...ADAV4601 System Design Document Confidential Information Rev 1 August 2009 Analog Devices Page 112...
