System Overview
3-11
RD
Read Strobe (output, synchronous, three-state)
RD—This pin indicates to the system that the microcontroller is
performing a memory or I/O read cycle. RD is guaranteed not to be
asserted before the address and data bus is floated during the address-
to-data transition. RD floats during a bus hold condition.
RES
Reset (input, asynchronous, level-sensitive)
This pin causes the microcontroller to perform a reset. When RES is
asserted, the microcontroller immediately terminates its present
activity, clears its internal logic, and CPU control is transferred to the
reset address FFFF0h. RES must be held Low for at least 1 ms. The
assertion of RES can be asynchronous to CLKOUTA because RES is
synchronized internally. For proper initialization, V
CC
must be within
specifications, and CLKOUTA must be stable for more than four
CLKOUTA periods during which RES is asserted. The microcontroller
begins fetching instructions approximately 6.5 CLKOUTA periods after
RES is deasserted. This input is provided with a Schmitt trigger to
facilitate power-on RES generation via an RC network.
RFSH2/ADEN
Refresh 2 (three-state, output, synchronous)
Address Enable (input, internal pullup)
RFSH2—Available on the Am188EM microcontroller only, RFSH2/
ADEN is asserted Low to signify a DRAM refresh bus cycle. The use
of RFSH2/ADEN to signal a refresh is not valid when PSRAM mode is
selected. Instead, the MCS3/RFSH signal is provided to the PSRAM.
ADEN—If RFSH2/ADEN is held High or left floating on power-on reset,
the AD bus (AO15–AO8 and AD7–AD0) is enabled or disabled during
the address portion of LCS and UCS bus cycles based on the DA bit in
the LMCS and UMCS registers. If the DA bit is set, the memory address
is accessed on the A19–A0 pins. This mode of operation reduces power
consumption. There is a weak internal pullup resistor on RFSH2/ADEN,
so no external pullup is required.
If RFSH2/ADEN is held Low on power-on reset, the AD bus drives both
addresses and data. The pin is sampled one crystal clock cycle after the
rising edge of RES. RFSH2/ADEN is three-stated during bus holds and
ONCE mode.
See section 5.5.1 and section 5.5.2 for additional information on
enabling and disabling the AD bus during the address phase of a bus
cycle.
RXD
Receive Data (input, asynchronous)
This pin supplies asynchronous serial receive data to the
microcontroller UART.
S2–S0
Bus Cycle Status (output, three-state, synchronous)
These pins indicate to the system the type of bus cycle in progress. S2
can be used as a logical memory or I/O indicator, and S1 can be used
as a data transmit or receive indicator. S2–S0 float during bus hold and
hold acknowledge conditions. The S2–S0 pins are encoded as shown
in the following table.
Содержание AM186EM
Страница 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...
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Страница 12: ...Table of Contents xii...
Страница 62: ...Peripheral Control Block 4 10...
Страница 76: ...Chip Select Unit 5 14...
Страница 122: ...Timer Control Unit 8 8...
Страница 136: ...DMA Controller 9 14...
Страница 144: ...Asynchronous Serial Port 10 8...
Страница 158: ...Programmable I O Pins 12 6...
Страница 186: ...Index I 12...