DMA Controller
9-5
9.3.2
DMA Transfer Count Registers (D0TC, Offset C8h, D1TC,
Offset D8h)
Each DMA channel maintains a 16-bit DMA Transfer Count register (DTC). This register
is decremented after every DMA cycle, regardless of the state of the TC bit in the DMA
Control register. However, if the TC bit in the DMA control word is set or if unsynchronized
transfers are programmed, DMA activity terminates when the Transfer Count register
reaches 0.
Figure 9-3
DMA Transfer Count Registers (D0TC, D1TC, offsets C8h and D8h)
The value of D0TC and D1TC at reset is undefined.
Bits 15–0: DMA Transfer Count (TC15–TC0)—Contains the transfer count for a DMA
channel. Value is decremented by 1 after each transfer.
15
7
0
TC15–TC0
Содержание AM186EM
Страница 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...
Страница 4: ...iv...
Страница 12: ...Table of Contents xii...
Страница 62: ...Peripheral Control Block 4 10...
Страница 76: ...Chip Select Unit 5 14...
Страница 122: ...Timer Control Unit 8 8...
Страница 136: ...DMA Controller 9 14...
Страница 144: ...Asynchronous Serial Port 10 8...
Страница 158: ...Programmable I O Pins 12 6...
Страница 186: ...Index I 12...