Table of Contents
vi
CHIP SELECT TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
READY AND WAIT-STATE PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 5-2
CHIP SELECT OVERLAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
CHIP SELECT REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.5.1
Upper Memory Chip Select Register (UMCS, Offset A0h) . . . . . . 5-4
Low Memory Chip Select Register (LMCS, Offset A2h) . . . . . . . . 5-6
Midrange Memory Chip Select Register (MMCS, Offset A6h) . . . 5-8
PCS and MCS Auxiliary Register (MPCS, Offset A8h) . . . . . . . . 5-10
Peripheral Chip Select Register (PACS, Offset A4h) . . . . . . . . . 5-12
Memory Partition Register (MDRAM, Offset E0h) . . . . . . . . . . . . 6-1
Clock Prescaler Register (CDRAM, Offset E2h) . . . . . . . . . . . . . . 6-2
Enable RCU Register (EDRAM, Offset E4h) . . . . . . . . . . . . . . . . 6-2
Definitions of Interrupt Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Interrupt Conditions and Sequence . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Software Exceptions, Traps, and NMI . . . . . . . . . . . . . . . . . . . . . . 7-6
Interrupt Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Interrupt Controller Reset Conditions . . . . . . . . . . . . . . . . . . . . . . 7-8
MASTER MODE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
Cascade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Special Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Operation in a Polled Environment . . . . . . . . . . . . . . . . . . . . . . . 7-11
End-of-Interrupt Write to the EOI Register . . . . . . . . . . . . . . . . . 7-11
MASTER MODE INTERRUPT CONTROLLER REGISTERS . . . . . . . . 7-12
INT4 Control Register (I4CON, Offset 40h) (Master Mode) . . . . 7-16
7.3.10 Priority Mask Register (PRIMSK, Offset 2Ah) (Master Mode). . . 7-23
7.3.11 Interrupt Mask Register (IMASK, Offset 28h) (Master Mode) . . . 7-24
7.3.12 Poll Status Register (POLLST, Offset 26h) (Master Mode). . . . . 7-25
7.3.13 Poll Register (POLL, Offset 24h) (Master Mode). . . . . . . . . . . . . 7-26
7.3.14 End-of-Interrupt Register (EOI, Offset 22h) (Master Mode) . . . . 7-27
SLAVE MODE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
Содержание AM186EM
Страница 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...
Страница 4: ...iv...
Страница 12: ...Table of Contents xii...
Страница 62: ...Peripheral Control Block 4 10...
Страница 76: ...Chip Select Unit 5 14...
Страница 122: ...Timer Control Unit 8 8...
Страница 136: ...DMA Controller 9 14...
Страница 144: ...Asynchronous Serial Port 10 8...
Страница 158: ...Programmable I O Pins 12 6...
Страница 186: ...Index I 12...