Interrupt Control Unit
7-18
7.3.5
Watchdog Timer Interrupt Control Register (WDCON, Offset 42h)
(Master Mode)
The Am186EM and Am188EM microcontrollers provide an additional on-chip interrupt
source, the watchdog timer. This timer is constructed from existing 80C186 microcontroller
pins. It is implemented by connecting the TMROUT1 output to an additional internal interrupt
to create the watchdog timer interrupt. This interrupt is assigned to interrupt type 11h. The
control register format is shown in Figure 7-8.
The systems programmer should program the timer (see section 8.2.2 on page 8-3) and
then program the interrupt pin.
Figure 7-8
Watchdog Timer Interrupt Control Register (WDCON, offset 42h)
The value of WDCON at reset is 000Fh.
Bits 15–5: Reserved—Set to 0.
Bit 4: Reserved—
Must be set to 0 to ensure proper operation of the Am186EM and
Am188EM microcontrollers.
Bit 3: Mask (MSK)—This bit determines whether the watchdog timer can cause an interrupt.
A 1 in this bit masks this interrupt source, preventing the watchdog timer from causing an
interrupt. A 0 in this bit enables watchdog timer interrupts.
This bit is duplicated in the Interrupt Mask register. See the Interrupt Mask register in section
7.3.11 on page 7-24.
Bits 2–0: Priority (PR)—This field determines the priority of the watchdog timer relative
to the other interrupt signals, as shown in Table 7-3 on page 7-14.
15
7
0
Reserved
MSK
PR2
PR1
PR0
Содержание AM186EM
Страница 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...
Страница 4: ...iv...
Страница 12: ...Table of Contents xii...
Страница 62: ...Peripheral Control Block 4 10...
Страница 76: ...Chip Select Unit 5 14...
Страница 122: ...Timer Control Unit 8 8...
Страница 136: ...DMA Controller 9 14...
Страница 144: ...Asynchronous Serial Port 10 8...
Страница 158: ...Programmable I O Pins 12 6...
Страница 186: ...Index I 12...