System Overview
3-20
The refresh control unit must be programmed before accessing PSRAM in LCS space. The
refresh counter in the Clock Prescaler (CDRAM) register must be configured with the
required refresh interval value. The ending address of LCS space and the ready and wait-
state generation in the LMCS register must also be programmed.
The refresh counter reload value in the CDRAM register should not be set to less than 18
(12h) in order to provide time for processor cycles within refresh. In PSRAM mode, the
refresh address counter must be set to 0000h to prevent another chip select from asserting.
LCS is held High during a refresh cycle. The A19–A0 bus is not used during refresh cycles.
The LMCS register must be configured to external Ready ignored (R2=1) with one wait
state (R1–R0=01b), and the PSRAM mode enable bit (PSE) must be set to 1. See section
5.5.2 on page 5-6.
3.4
CLOCK AND POWER MANAGEMENT UNIT
The clock and power management unit of the Am186EM and Am188EM microcontrollers
includes a phase-locked loop (PLL) and a second programmable system clock output
(CLKOUTB).
3.4.1
Phase-Locked Loop (PLL)
In a traditional 80C186/188 design, the crystal frequency is twice that of the desired internal
clock. Because of the internal PLL on the Am186EM and Am188EM microcontrollers, the
internal clock generated by the microcontroller (CLKOUTA) is the same frequency as the
crystal. The PLL takes the crystal inputs (X1 and X2) and generates a 45/55% (worst case)
duty cycle intermediate system clock of the same frequency. This feature removes the need
for an external 2x oscillator, thereby reducing system cost. The PLL is reset during power-
on reset by an on-chip power-on reset (POR) circuit.
3.4.2
Crystal-Driven Clock Source
The internal oscillator circuit of the microcontroller is designed to function with a parallel
resonant fundamental or third overtone crystal. Because of the PLL, the crystal frequency
is equal to the processor frequency. Replacement of a crystal with an LC or RC equivalent
is not recommended.
The X1 and X2 signals are connected to an internal inverting amplifier (oscillator) which
provides, along with the external feedback loading, the necessary phase shift (Figure 3-5).
In such a positive feedback circuit, the inverting amplifier has an output signal (X2) 180
degrees out of phase of the input signal (X1). The external feedback network provides an
additional 180-degree phase shift. In an ideal system, the input to X1 will have 360 or zero
degrees of phase shift.
The external feedback network is designed to be as close as possible to ideal. If the
feedback network is not providing necessary phase shift, negative feedback will dampen
the output of the amplifier and negatively affect the operation of the clock generator. Values
for the loading on X1 and X2 must be chosen to provide the necessary phase shift and
crystal operation.
Содержание AM186EM
Страница 1: ...Am186 EM and Am188 EM Microcontrollers User s Manual...
Страница 4: ...iv...
Страница 12: ...Table of Contents xii...
Страница 62: ...Peripheral Control Block 4 10...
Страница 76: ...Chip Select Unit 5 14...
Страница 122: ...Timer Control Unit 8 8...
Страница 136: ...DMA Controller 9 14...
Страница 144: ...Asynchronous Serial Port 10 8...
Страница 158: ...Programmable I O Pins 12 6...
Страница 186: ...Index I 12...