Stratix II Memory Board 2 Rev A User Guide Rev 0.1
Altera Confidential
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This section describes the QDRII SRAM Devices test. Refer to “QDRII SRAM
Device(s)” in section 3.1.8 for information on how to perform the test. The QDRII
SRAM test uses the Altera® QDRII SRAM MegaCore® function, the example driver
provided with the MegaCore function, and some logic to indicate the status of the test.
This test reads and writes pseudo-random binary sequence (PRBS) data to and from the
QDRII SRAM. The MegaCore function also includes a testbench, and simulation
instructions.
The QDRII SRAM test uses a hardware state machine included in the QDRII
MegaCore® function, and four DDR2 SDRAM devices to test the DDR2 SDRAM
interface.
The example driver is a self-test module that issues read and write commands to the
controller, and checks the read data to produce the pass/fail and test complete signals.
The example driver generates a pseudo-random binary sequence (PRBS) that is written to
the DDR2 SDRAM devices, then read back and compared with the transmitted data. The
test reads and writes across the entire address range of the DDR2 SDRAM Devices. The
board has been tested with four DDR2 SDRAM devices operating at once.
• Cypress Semiconductor CY7C1313AV18-250BZC
• Samsung Semiconductor K4H561638F-TCCC
Refer to the DDR2 & DDR2 SDRAM Controller Compiler User Guide for information
regarding the example driver and the DDR2 SDRAM MegaCore function.
