![Advantech SOM-4450 Series Скачать руководство пользователя страница 84](http://html1.mh-extra.com/html/advantech/som-4450-series/som-4450-series_design-manual_2857982084.webp)
Advantech SOM-ETX Design Guide
Digital GND
Chassis GND
TTL LCD
Connector
120 Ohm
@100MHz
SOM-ETX
10~33 Ohm
VGA
Damping
TTL
10pF
Buffer IC
for Level
Shift
Carryboard
BACKON
Inverter
Connector
LCDON
VDD
Power
Transfer
+3.3V
+5V
Bead
30Ohm
@100Mhz
Figure 5-21 TTL LCD Layout Guideline
5.7 IDE0/IDE1
SOM-ETX provides two IDE interface, IDE0/IDE1.
5.7.1 Signal Description
Table 5.15 shows SOM-ETX PCI IDE signals, including pin number, signals, I/0 and
descriptions.
Table 5.15 IDE signals description
Pin Signal
I/O
Description
-
PIDE_D[0..15]
SIDE_D[0..15]
I/O
Primary/ Secondary IDE ATA Data Bus. These are the Data
pins connected to Primary Channel.
D38,40,3
6
D31,37,2
9
PIDE_A[0..2]
SIDE_A[0..2]
O
IDE ATA Address Bus. These are the Address pins
connected to Secondary Channel.
D32
D27
PIDE_CS#1
SIDE_CS#1
O
IDE Chip Select 1 for Channel 0. This is the Chip Select 1
command output pin to enable the IDE device to watch the
Read/Write Command.
D30
D25
PIDE_CS#3
SIDE_CS#3
O
IDE CHIP SELECT 3 FOR CHANNEL 1. THIS IS THE CHIP
SELECT 3 COMMAND OUTPUT PIN TO ENABLE THE IDE
DEVICE TO WATCH THE READ/WRITE COMMAND
D56
D53
PIDE_DRQ
SIDE_DRQ
I
IDE DMA Request for IDE Master. This is the input pin from
the IDE DMA request to do the IDE Master Transfer. It will
active high in DMA or Ultra-33 mode and always be inactive
low in PIO mode.
D46
D43
PIDE_ACK#
SIDE_ACK#
O
IDE_ACK# for IDE Master. This is the output pin to grant the
IDE DMA request to begin the IDE Master Transfer in DMA
or Ultra-33 mode.
D46
D45
PIDE_RDY
SIDE_RDY
I
IDE Ready. This is the input pin from the IDE Channel to
indicate the IDE device is ready to terminate the IDE
command in PIO mode. The IDE device can de-assert this
input (logic 0) to expand the IDE command if the device is
not ready. In Ultra-33 mode, this pin has different functions.
In read cycle, IDE device will drive this signal as Data Strobe
(DSTROBE) to use by IDE Bus master to strobe the input
data. In write cycles, this pin is used by IDE device to notify
IDE Bus master as DMA Ready.
D52
D47
PIDE_IOR#
SIDE_IOR#
O
IDE_IOR# Command. This is the IOR# command output pin
to notify the IDE device to assert the Read Data in PIO and
DMA mode. In Ultra-33 mode, this pin has different function.
In read cycle, this pin is used by IDE-Bus-master to notify
84
Chapter 5 Carrier Board Design Guidelines
Содержание SOM-4450 Series
Страница 1: ...Advantech SOM ETX Series System On Modules Design Guide Version 1 0...
Страница 105: ...Advantech SOM ETX Design Guide Figure 5 39 TV DAC Signal Routing Spacing Chapter 5 Carrier Board Design Guidelines 105...
Страница 130: ...Advantech SOM ETX Design Guide 130 Chapter 8 Heat Sink Recommended Design...