Advantech SOM-ETX Design Guide
SOM-ETX
Module
Pin 77
Pin 78
Pin 75
Pin 73
Pin 97
Pin 98
Pin 95
Pin 93
PCI Slot / Device 1
PCI Slot / Device 2
PCI Slot / Device 3
PCI Slot / Device 4
Pin A26
IDSEL
Pin A26
IDSEL
Pin A26
IDSEL
Pin A26
IDSEL
Pin A6
Pin B7
Pin A7
Pin B8
Pin A6
Pin A6
Pin A6
Pin B7
Pin B7
Pin B7
Pin A7
Pin A7
Pin A7
Pin B8
Pin B8
Pin B8
AD22
AD21
AD20
AD19
INTC#
INTD#
INTA#
INTB#
Figure 5-1 Routing PCI Slot/Device CSB Interrupt
Due to different system configurations, IRQ line routing to the PCI slots should be
made to minimize the sharing of interrupts between both internal chipset functions
and PCI functions. However, the INTA# pin of the device should not necessarily be
connected to the SOM-ETX INTA# signal. Refer to Chapter 2.X.X System Interrupt
for the details.
5.1.2.2 PCI Clock and Clock Skew
The trace length for all PCI clocks should be matched and controlled. PCI clock
routes should be separated as far from other signal traces as possible. PCI clock
signals should be routed as controlled-impedance traces, with trace impedance 55
Ohm . Only one PCI device or slot should be driven from each SOM-ETX PCI clock
output.
The maximum allowable clock skew is 2 ns. This specification applies not only at a
single threshold point, but at all points on the clock edge that fall in the switching
range. The maximum skew is measured between any two components rather than
between connectors. To correctly evaluate clock skew, the system designer must
take into account clock distribution on the add-in card.
Table 5.3 Clock Skew Parameters
Symbol
3.3V Signaling
5V Signaling
Units
Vtest 0.4Vcc
1.5 V
Tskew 2(max) 2(max) ns
Chapter 5 Carrier Board Design Guidelines
63
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