ADLINK Technology DAQ-20 Series, Руководство пользователя

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Operation Theory
4.3 Digital I/O
The DAQ/PXI-20XX contains 24-lines of general-purpose digital I/O
(GPIO), which is provided through a 82C55A chip.
The 24-line GPIO are separated into three ports: Port A, Port B and Port C.
High nibble (bit[7…4]), and low nibble (bit[3…0]) of each port can be indi-
vidually programmed to be either inputs or outputs. Upon system startup
or reset, all the GPIO pins are reset to high impedance inputs.
DAQ/PXI-2010 also provides 2 digital inputs per channel (SDI from J5),
which are sampled simultaneously with an analog signal input and is stored
with the 14-bit AD data. Please refer to section 4.1.1.1 for the more details.
4.4 General Purpose Timer/Counter Operation
Two independent 16-bit up/down timer/counter are designed within FPGA
for various applications. They have the following features:
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Count up/down controlled by hardware or software
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Programmable counter clock source (internal or external clock up to
10MHz)
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Programmable gate selection (hardware or software control)
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Programmable input and output signal polarities (high active or low
active)
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Initial Count can be loaded from software
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Current count value can be read-back by software without affecting
circuit operation
4.4.1 Timer/Counter functions basics
Each timer/counter has three inputs that can be controlled via hardware or
software. They are clock input (GPTC_CLK), gate input (GPTC_GATE),
and up/down control input (GPTC_UPDOWN). The GPTC_CLK input
provides a clock source input to the timer/counter. Active edges on the
GPTC_CLK input make the counter increment or decrement. The
GPTC_UPDOWN input controls whether the counter counts up or down.
The GPTC_GATE input is a control signal which acts as a counter enable
or a counter trigger signal under different applications.
The output of timer/counter is GPTC_OUT. After power-up, GPTC_OUT is
pulled high by a pulled-up resister about 10K ohms. Then GPTC_OUT
goes low after the DAQ/PXI-20XX is initialized.