Introduction
•
5
•
CMRR:
(DC to 60Hz, Typical)
Device
Input Range
CMRR
Input Range
CMRR
±
10V
90 dB
0~10V
89 dB
±
5V
92 dB
0~5V
92 dB
±
2.5V
95 dB
0~2.5V
94 dB
2010
±
1.25V
97 dB
0~1.25V
97 dB
±
10V
86 dB
0~10V
85 dB
±
5V
88 dB
0~5V
88 dB
±
2.5V
91 dB
0~2.5V
90 dB
2005
±
1.25V
93 dB
0~1.25V
93 dB
±
10V
87 dB
0~10V
86 dB
±
5V
89 dB
0~5V
88 dB
±
2.5V
91 dB
0~2.5V
91 dB
2006
±
1.25V
93 dB
0~1.25V
93 dB
Table 3: CMRR: (DC to 60Hz)
•
Time-base source:
Internal 40MHz or External clock Input (fmax: 40MHz, fmin: 1MHz,
50% duty cycle)
•
Trigger modes:
Post-trigger, Delay-trigger, Pre-trigger and Middle-trigger
•
Data transfers:
Programmed I/O, and bus -mastering DMA with scatter/gather
•
Input coupling:
DC
•
Offset error:
Before calibration:
±
60mV max
After calibration:
±
1mV max
•
Gain error:
Before calibration:
±
0.6% of output max
After calibration:
±
0.1% of output max for DAQ/PXI-2010
±
0.03% of output max for DAQ/PXI-2005/2006