SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE
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5. Clear pending interrupts by writing a “1” to each channel’s
respective bit in the Interrupt Status Register.
Interrupts can now be generated by matching the input level with
the selected polarity for programmed interrupt channels.
General Sequence of Events for Processing an Interrupt
1. The IP1K100 asserts the Interrupt Request 0 Line (INTREQ0
∗
)
in response to an interrupt condition at one or more inputs.
2. The AVME9630/9660 carrier board acts as an interrupter in
making the VMEbus interrupt request (asserts IRQx
∗
)
corresponding to the IP interrupt request.
3. The VMEbus host (interrupt handler) asserts IACK
∗
and the
level of the interrupt it is seeking on A01-A03.
4. When the asserted VMEbus IACKIN
∗
signal (daisy-chained) is
passed to the AVME9630/9660, the carrier board will check if
the level requested matches that specified by the host. If it
matches, the carrier board will assert the INTSEL
∗
line to the
appropriate IP together with (carrier board generated) address
bit A1 to select which interrupt request is being processed (A1
low corresponds to IntReq0
∗
; A1 high corresponds to
INTREQ1
∗
.
5. The IP1K100 puts the appropriate interrupt vector on the local
data bus (D00-D07 for the D08 [O] interrupter) and asserts
ACK
∗
to the carrier board. The carrier board passes this along
to the VMEbus (D08[O]) and asserts DTACK
∗
.
6. The host uses the vector to form a pointer to an interrupt service
routine for the interrupt handler to begin execution.
7. Example of Generic Interrupt Handler Actions:
A. Disable the interrupting IP by writing “0” to the appropriate
bit in the AVME9630/9660 IP Interrupt Enable Register.
B. Disable the interrupting channel(s) by writing a “0” to the
appropriate bits in the IP1K100 Interrupt Enable Register.
C. Clear the interrupting channel(s) by writing a “1” to the
appropriate bits in the IP1K100 Interrupt Status Register.
D. Enable the interrupting channel(s) by writing a “1” to the
appropriate bits in the IP1K100 Interrupt Enable Register.
E. Clear the interrupting IP by writing a “1” to the appropriate
bit in the AVME9630/9660 IP Interrupt Clear Register.
F. Enable the interrupting IP by writing a “1” to the appropriate
bit in the AVME9630/9660 IP Interrupt Enable Register.
8. If the IP1K100 interrupt stimulus has been removed and no other
IP modules have interrupts pending, the interrupt cycle is
complete (i.e. the carrier board negates its interrupt request,
IRQ
∗
).
A. If the IP1K100 interrupt stimulus remains, a new interrupt
request will immediately follow. If the stimulus cannot be
removed, the IP1K100 should be disabled or reconfigured.
B. If other IP modules have interrupts pending, then the
interrupt request (IRQx
∗
) will remain asserted. This will
start a new interrupt cycle.
4.0 THEORY OF OPERATION
This section describes the basic functionality of the circuitry
used on the board. Refer to the Block Diagram shown in Drawing
4501-908 as you review this material.
FIELD INPUT/OUTPUT SIGNALS
The field I/O interface to the IP module is provided through
connector P2 (refer to Table 2.1). These pins are tied to the inputs
and outputs of EIA RS485/RS422 line transceivers or TTL
transceivers. RS485 signals received are converted from the
required EIA RS485/RS422 voltages signals to the TTL levels
required by the FPGA. Likewise TTL signals are converted to the
EIA RS485/RS422 voltages for data output transmission. The
FPGA provides the necessary interface to the RS485/RS422
transceivers or TTL transceivers for control of data output or input
and monitoring of input signals for generation of interrupts, if
enabled.
The field I/O interface to the carrier board is provided through
connector P2 (refer to Table 2.1). Field I/O points are NON-
ISOLATED. This means that the field return and logic common
have a direct electrical connection to each other. As such, care
must be taken to avoid ground loops (see Section 2 for connection
recommendations). Ignoring this effect may cause operational
errors, and with extreme abuse, possible circuit damage.
LOGIC/POWER INTERFACE
The logic interface to the carrier board is made through
connector P1 (refer to Table 2.3). P1 also pr5V power the
module (
±
12V is not used). Note that the ERROR
∗
signal is not
used.
An FPGA installed on the IP Module provides an interface to the
carrier board per IP Module specification ANSI/VITA 4 1995. The
supplied FPGA logic example includes: address decoding, I/O and
ID read/write control circuitry, interrupt handling, and ID storage
implementation.
Address decoding of the six IP address signals A(1:6) is
implemented in the FPGA, in conjunction with the IP select signals,
to identify access to the IP module’s ID or I/O space. In addition, the
byte strobes BS0
∗
and BS1
∗
are decoded to identify low byte, high
byte, or double byte data transfers.
The carrier to IP module interface allows access to both ID and
I/O space via 16 or 8-bit data transfers. Read only access to ID
space provides the identification for the individual module (as given
in Table 3.2) per the IP specification. Read and write accesses to
the I/O space provide a means to control the IP1K100.
The IP1K100 has 64K words of SRAM available. Read and
write accesses to the SRAM are implemented through the IP module
I/O space. A start address is specified in the Memory Address
register. This start address will automatically be incremented by
hardware for each access to the Memory Data register.
The IP1K100 also has a Clock Generator chip. A clock
frequency from 391KHz to 100MHz is programmable via the IP
module I/O space. The generated clock frequency is input to the
FPGA on pin 183. This clock can be used to synchronize I/O
operations with other IP modules.
Interrupt Operation
For the supplied FPGA configuration, digital input channels of
this model can be configured to generate interrupts for Change-Of-
State (COS) and input level (polarity) match conditions at enabled
inputs. An 8-bit interrupt service routine vector is provided during
interrupt acknowledge cycles on data lines D0...D7. The interrupt
release mechanism employed is RORA (Release On Register
Access).
