SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE
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specified by the Interrupt Polarity Register occurs (i.e. Low or High
level transition interrupt). A “1” bit means the interrupt will occur
when a Change-Of-State (COS) occurs at the corresponding input
channel (i.e. any state transition, low to high or high to low).
The Interrupt Type Configuration register at the carrier’s base
a offset 0DH is used to control channels 00 through 07.
For example, channel 00 is controlled via data bit-0 as seen in the
table below.
Interrupt Type (COS or H/L) Configuration Register
MSB
LSB
Data
Bit
07
Data
Bit
06
Data
Bit
05
Data
Bit
04
Data
Bit
03
Data
Bit
02
Data
Bit
01
Data
Bit
00
Ch07
Ch06
Ch05
Ch04
Ch03
Ch02
Ch01
Ch00
Channel read or write operations use 8-bit, or 16-bit data
transfers. The upper 8 bits of this register are “Not Used” and will
always read low (0’s) for D16 accesses. Note that interrupts will not
occur unless they are enabled.
All bits are set to “0” following a reset which means that, if
enabled, the inputs will cause interrupts for the levels specified by
the digital input channel Interrupt Polarity Register.
Interrupt Status Registers (Read/Write) - (Base + 0FH)
The Interrupt Status Register reflects the status of each of the
interrupting channels. A “1” bit indicates that an interrupt is pending
for the corresponding channel. A channel that does not have
interrupts enabled will never set its interrupt status flag. A channel’s
interrupt can be cleared by writing a “1” to its bit position in the
Interrupt Status Register (writing a “1” acts as a reset signal to clear
the set state). This is known as the “Release On Register Access”
(RORA) method, as defined in the VME system architecture
specification. However, if the condition which caused the interrupt to
occur remains, the interrupt will be generated again (unless disabled
via the Interrupt Enable Register). In addition, an interrupt will be
generated if any of the channels enabled for interrupt have an
interrupt pending (i.e. one that has not been cleared). Writing “0” to
a bit location has no effect; that is, a pending interrupt will remain
pending.
Note that interrupts are not prioritized via hardware. The system
software must handle interrupt prioritization.
The Interrupt Status register at the carrier’s base a
offset 0FH is used to monitor pending interrupts corresponding to
channels 00 through 07. For example, channel 00 is monitored via
data bit-0 as seen in the table below.
Interrupt Status Register
MSB
LSB
Data
Bit
07
Data
Bit
06
Data
Bit
05
Data
Bit
04
Data
Bit
03
Data
Bit
02
Data
Bit
01
Data
Bit
00
Ch07
Ch06
Ch05
Ch04
Ch03
Ch02
Ch01
Ch00
The unused upper 8 bits of this register are “Not Used” and will
always read low (0’s) for D16 accesses. All bits are set to “0”
following a reset which means that all interrupts are cleared.
Interrupt Polarity Registers (Read/Write) - (Base + 11H)
The Interrupt Polarity Register determines the level that will
cause a channel interrupt to occur for each of the channels enabled
for level interrupts. A “0” bit specifies that an interrupt will occur
when the corresponding input channel is low (i.e. a “0” in the digital
input channel data register). A “1” bit means that an interrupt will
occur when the input channel is high (i.e. a “1” in the digital input
channel data register). Note that no interrupts will occur unless they
are enabled by the Interrupt Enable Register. Further, the Interrupt
Polarity Register will have no effect if the Change-of-State (COS)
interrupt type is configured by the Interrupt Type Configuration
Register.
The Interrupt Polarity register at the carriers base a
offset 11H is used to control channels 00 through 07. For example,
channel 00 is controlled via data bit-0 as seen in the table below.
Interrupt Polarity Register
MSB
LSB
Data
Bit
07
Data
Bit
06
Data
Bit
05
Data
Bit
04
Data
Bit
03
Data
Bit
02
Data
Bit
01
Data
Bit
00
Ch07
Ch06
Ch05
Ch04
Ch03
Ch02
Ch01
Ch00
The upper 8 bits of this register are “Not Used” and will always
read low (0’s) for D16 accesses. All bits are set to “0” following a
reset which means that the inputs will cause interrupts when they
are below TTL threshold (provided they are enabled for interrupt on
level).
Interrupt Vector Register (Read/Write) - (Base + 13H)
The Interrupt Vector Register maintains an 8-bit interrupt pointer
for all channels configured as input channels. The Vector Register
can be written with an 8-bit interrupt vector. This vector is provided
to the carrier and system bus upon an active INTSEL
∗
cycle.
Reading or writing to this register is possible via 16-bit or 8-bit data
transfers.
Interrupt Vector Register
MSB
LSB
07
06
05
04
03
02
01
00
Interrupts are released on register access to the Interrupt Status
register. Issue of a software or hardware reset will clear the
contents of this register to 0.
Memory Data Register (Read/Write, 14H)
The Memory Data register is used to provide read or write
access to SRAM memory. Reading or writing to this register is
possible via 16-bit data transfers only.
In order to properly access the memory, which constitutes 64K
words, an address pointer to a single word in memory must first be
specified. The address is specified via the Memory Address
register. The value written into the Memory Address register is used
to point to one of the 64K words.
All read or write accesses to the Memory Data register will in
turn implement an access to memory at the address specified by the
Memory Address register.
