SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE
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9.
Write 0x2 to the Trigger register at Base A 1FH to
start the serial shift of the control word to the Clock Generator
chip.
For more information about the Clock Generator chip, refer to
the ICD2053B data sheet available from Cypress at
www.cypress.com.
IP1K100 PROGRAMMING CONSIDERATIONS
Acromag provides a software product (sold separately)
consisting of IP module ActiveX (OLE) controls for Windows 98,
95
, ME, 2000, XP, and Windows NT
compatible application
programs (Model IPSW-ATX-PCI, MSDOS format). This software
provides individual controls that allow Acromag IP modules to be
easily integrated into Windows
application programs, such as
Visual C++
, Visual Basic
, Microsoft
Office
97 applications
and others. The ActiveX controls provide a high-level interface to IP
modules, eliminating the need to perform low-level reads/writes of
registers, and the writing of interrupt handlers—all the complicated
details of programming are handled by the ActiveX controls. The
ActiveX control IP1K100 support programs implement the transfer of
developed code between the user’s processor and the Altera FPGA.
These functions are intended for use in conjunction with an
Acromag personal computer carrier and consist of an ActiveX
Carrier Control, and an ActiveX control for each Acromag IP module,
as well as, a generic control for non-Acromag IP modules.
IP MODULE VxWORKS SOFTWARE
Acromag provides a software product (sold separately)
consisting of IP module VxWorks
libraries. This software (Model
IPSW-API-VXW MSDOS format) is composed of VxWorks
(real
time operating system) libraries for all Acromag IP modules and
carriers including the AVME9670, AVME9660/9630, APC8620/21,
ACPC8630/35, and ACPC8625. The software is implemented as a
library of “C” functions which link with existing user code to make
possible simple control of all Acromag IP modules and carriers. The
IP1K100 support programs implement the transfer of developed
code between the user’s processor and the Altera FPGA.
Programming Interrupts
Digital input channels can be programmed to generate interrupts
for the following conditions:
•
Change-of-State (COS) at selected input channels.
•
Input level (polarity) match at selected input channels.
Interrupts generated by the IP1K100 use interrupt request line
INTREQ0
∗
(Interrupt Request 0). The interrupt release mechanism
employed is the Release On Register Access (RORA) type. This
means that the interrupter will release the Industrial I/O Pack
interrupt request line (INTREQ0) after all pending interrupts have
been cleared by writing a “1” to the appropriate bit positions in the
input channel Interrupt Status Register.
In VMEbus systems, the Interrupt Vector Register contains a
pointer vector to an interrupt handling routine. One interrupt
handling routine must be used to service all possible channel
interrupts.
When using interrupts, input channel bandwidth should be
limited to reduce the possibility of missing channel interrupts. For a
given input channel, this could happen if multiple changes occur
before the channel’s interrupt is serviced. The response time of the
input channels should also be considered when calculating this
bandwidth. The total response time is the sum of the input buffer
response time, plus the interrupt logic circuit response time, and this
time must pass before another interrupt condition will be recognized.
The Interrupt Input Response Time is specified in section 6.
The following programming examples assume that the IP1K100
is installed onto an Acromag AVME9630/9660 carrier board (consult
your carrier board documentation for compatibility details).
Programming Example for AVME9630/9660 Carrier Boards:
1. Clear the global interrupt enable bit in the Carrier Board Status
Register by writing a “0” to bit 3.
2. Perform Specific IP Module Programming - see the Change-of-
State or Level Match programming examples that follow, as
required for your application.
3. Write to the carrier board Interrupt Level Register to program the
desired interrupt level per bits 2, 1, & 0.
4. Write “1” to the carrier board IP Interrupt Clear Register
corresponding to the IP interrupt request(s) being configured.
5. Write “1” to the carrier board IP Interrupt Enable Register bits
corresponding to the IP interrupt request to be enabled.
6. Enable interrupts from the carrier board by writing a “1” to bit 3
(the Global Interrupt Enable Bit) of the Carrier Board Status
Register.
Programming Example for Change-of-State Interrupts:
1. Program the Interrupt Vector Register with the user specified
interrupt vector. This vector forms a pointer to a location in
memory that contains the address of the interrupt handling
routine.
2. Select channel Change-of-State interrupts by writing a “1” to
each channel’s respective bit in the Interrupt Type Register.
Note that Change-Of-State interrupts (specified with “1”) may be
mixed with polarity match interrupts (specified with “0”).
3. Enable individual input channel interrupts by writing a “1” to
each channel’s respective bit in the Interrupt Enable Register.
4. Clear pending interrupts by writing a “1” to each channel’s
respective bit in the Interrupt Status Register.
Change-of-State Interrupts may now be generated by the input
channels programmed above for any Change-Of-State
transition.
Programming Example for Level (Polarity) Match Interrupts:
1. Program the Interrupt Vector Register with the user specified
interrupt vector. This vector forms a pointer to a location in
memory that contains the address of the interrupt handling
routine.
2. Select channel polarity match interrupts by writing a “0” to each
channel’s respective bit in the Interrupt Type Registers. Note
that Change-Of-State interrupts (specified with “1”) may be
mixed with polarity match interrupts (specified with “0”).
3. Select the desired polarity (High/Low) level for interrupts by
writing a “0” (Low), or “1” (High) level to each channel’s
respective bit in the Interrupt Polarity Registers.
4. Enable individual input channel interrupts by writing a “1” to
each channel’s respective bit in the Interrupt Enable Registers.
