SERIES IP1K100 INDUSTRIAL I/O PACK RECONFIGURABLE DIGITAL I/O MODULE
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The example design supplied with the IP1K100 is provided as a
VHDL file for Altera’s Max+Plus II software. The example design
includes an IP bus interface to ID space, IO space and Interrupt
space. IO space is used to access a 64K x 16 RAM array, control
field data I/O, and control a clock generation chip.
The IP1K100 utilizes state of the art Surface-Mounted
Technology (SMT) to achieve its high channel density and is an ideal
choice for a wide range of industrial control and monitor applications
that require high-density, high-reliability, and high-performance at a
low cost.
KEY IP1K100 FEATURES
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Reconfigurable Altera FPGA – In system configuration of a
100,000 gate FPGA is implemented via the IP bus interface.
This provides a means for implementation of custom user
defined digital designs.
•
IP Bus Interface – The Altera FPGA is directly connected to
all IP bus logic signals. Custom designs can thus support all
IP module access types including ID, I/O, Interrupt, Memory,
and DMA.
•
High Channel Count Digital Interface – Differential and TTL
interface options are allowed. Interfaces with up to 24
differential, or a mix of 12 differential and 24 TTL, or up to 48
TTL digital input/output channels.
•
Channel Input/Output Control – The bidirectionality of the
TTL digital channels is controlled in groups of 8 channels. The
bidirectionality of the differential digital signals is controlled in
groups of 4 channels.
•
Long Distance Data Transmission – Data transmission with
RS485/RS422 Transceivers allow up to 32 nodes and up to
4000 feet of transmission cable.
•
64K x 16 SRAM – A 64K x 16 static random access memory
(SRAM) is directly accessed by the Altera device. Custom
user defined design logic for the Altera FPGA will permit use of
the SRAM as FIFO memory, or single port memory as required
by the application.
•
Example Design Provided – Example VHDL design which
includes implementation of the IP bus interface and control of
digital I/O with software programmable Interrupts is provided.
•
Clock Speed – Supports an 8 or 32 MHz IP bus clock speed.
•
Programmable Clock Generator – A clock generator IC is
provided for applications requiring a custom user specified
clock frequency. The clock generator can be programmed to
any desired frequency value between 391KHz and 100MHz.
•
No Configuration Jumpers or Switches – All configuration
is performed through software commands with no internal
jumpers to configure or switches to set.
•
Power Up & System Reset is Failsafe – For safety, all
channels are configured as input upon power-up and after a
system reset.
INDUSTRIAL I/O PACK INTERFACE FEATURES
•
High density - Single-size, industry-standard, IP module
footprint. Up to four units may be mounted on a 6U VMEbus
carrier board or five units may be mounted on a PCI carrier
board.
•
Local ID - Each IP module has its own 8-bit ID information
which is accessed via data transfers in the "ID Read" space.
•
16-bit & 8-bit I/O - Channel register Read/Write is performed
through D16 or D08 (EO) data transfer cycles in the IP module
I/O space.
•
High Speed - Access times for all data transfer cycles are
described in terms of "wait" states. For the supplied IP module
example, wait states are utilized for all read and write
operations (see specifications for detailed information).
SIGNAL INTERFACE PRODUCTS
(See Appendix for more information on compatible products)
This IP module will mate directly to any industry standard IP
carrier board (including Acromag’s AVME9630/60/70/75 VMEbus,
APC8610 ISA bus, APC8620/21 PCI bus, and ACPC8625/30/35
Compact PCI bus non-intelligent carrier boards). A wide range of
other Acromag IP modules are also available to serve your signal
conditioning and interface needs.
The cables and termination panels, described in the following
paragraphs, represent some of the accessories available from
Acromag. Each Acromag carrier has its own unique accessories.
They are not all listed in this document. Consult your carrier board
documentation for the correct interface product part numbers to
ensure compatibility with your carrier board.
Cables:
Model 5025-551-X (Shielded Cable), or Model 5025-550-X
(Non-Shielded Cable): A Flat 50-pin cable with female
connectors at both ends for connecting AVME9630/9660, or
other compatible carrier boards, to Model 5025-552 termination
panels. The unshielded cable is recommended for digital I/O,
while the shielded cable is recommended for optimum
performance with precision analog I/O applications.
Termination Panel:
Model 5025-552: A DIN-rail mountable panel that provides 50
screw terminals for universal field I/O termination. Connects to
all Acromag carriers (or other compatible carrier boards) via flat
50-pin ribbon cable (Model 5025-550-X or 5025-551-X).
Transition Module:
Model TRANS-GP: This module repeats field I/O connections
of IP modules A through D for rear exit from a VMEbus card
cage. It is available for use in card cages which provide rear exit
for I/O connections via transition modules (transition modules
can only be used in card cages specifically designed for them).
It is a double-height (6U), single-slot module with front panel
hardware adhering to the VMEbus mechanical dimensions,
except for shorter printed circuit board depth. It connects to
Acromag Termination Panel 5025-552 from the rear of the card
cage, and to AVME9630/9660 boards within the card cage, via
flat 50-pin ribbon cable (Model 5025-550-X or 5025-551-X).
IP1K100 FPGA ENGINEERING DESIGN KIT
Acromag provides an engineering design kit for the IP1K100
(sold separately), a “must buy” for first time IP1K100 module
purchasers. The design kit (model IP-1K100-EDK) provides the
user with the basic information required to develop a custom FPGA
program for download to the Altera FPGA. The design kit includes a
CD containing: schematics, parts list, part location drawing, example
VHDL source, example configuration file, and other utility files. The
IP1K100 is intended for users fluent in the use of Altera MaxPlus II
or Quartus design tools.
