Acorn FileStore E01, Руководство по обслуживанию

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Chapter 5 E01S Fault finding
FileStore Service Manual 72
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Y7(pin 7) low - enable IRQ
When Y7 is selected, the least significant bit of the data bus (D0) is clocked into a D-type
flip-flop (half of IC34). If this value is a one then the latch (2 NANDs of IC40) is enabled and
an IRQ will be generated at the next falling edge of REQ. To disable Interrupts Y7 is selected
with a 0 on D0. IRQs are enabled only for a very short time (around l0ms) when ensuring a
sequential file buffer.
4.9.1 Buffering
The data bus (DB0-DB7) is buffered in the write direction by the octal transparent latch IC38.
IC38 is enabled by Y4 of IC35 which is the write data signal. Due to IC38 being a transparent
latch, data will remain valid on the output side when the enable is deasserted. The outputs
from IC38 are gated through 8 open collector NAND buffers which are enabled from the I/O
control line of the FileStore expansion bus and which invert the bus signals.
The data bus is buffered and inverted in the read direction by an octal 3-state inverting buffer
which is enabled by Y0 of IC35 which is the read data signal.
4.9.2 Termination
The FileStore expansion bus is terminated by a resistor pack RP1 in the E01S and by an
external Termination pack placed in the FileStore expansion bus port of the unit at the other
end of the bus.
For more information about the operational phases of the FileStore expansion bus, refer to the
section entitled
Bus phases in Chapter 4 - Circuit Description in Part IV of this manual.
4.10 Main signal paths
4.10.1 Data bus
This is a 8 bit bi-directional bus emanating from the central processor, going to all the major
devices. The direction of the data flow is controlled by the CPU R/W line, a high level
indicating a read by the processor.
4.10.2 Address bus
This is a 16 bit uni-directional bus emanating from the central processor.
4.10.3 Address decoding
The main decoding components are IC3, ICl2, ICl3, and 1C17. These supply the decoding to
support the software activity as described below.
The layout of the file server memory map is as follows:
From To Function
0 &FF Zero page, see suballocation below
&100 &1ff Hardware stack
&200 &3FF MOS workspace
&400 &7BFF File server and print server code if loaded
&7C00 &E7FF File server and print server workspace
&E800 &FBFF MOS code
&FC00 &FCFF Memory mapped 1/0, see suballocation below
&FD00 &FFE2 MOS code