Acorn FileStore E01, Руководство по обслуживанию

Страница: 50 / 164

Chapter 4 E20 Circuit description
FileStore Service Manual 42
(1)
Target asserts REQ to request data transfer
(2) Initiator asserts ACK when data is valid on bus
(3) Target deasserts REQ when darn has been transferred
(4) Initiator deasserts ACK ready for next handshake
Prior to and during information transfer, the I/O signal determines the direction of the
transfer.
Before each information transfer phase the target will set up the MSG C/D and I/O lines in
such a
way that these control signals are stable for 450ns before the REQ of the first
handshake, and remain valid until the deassertion of ACK at the end of the last handshake.
During each information transfer phase the BSY line remains asserted and SEL deasserted.
Each information transfer phase is now described in turn.
Command phase
Allows the initiator to direct the subsequent action of the target by transferring command
bytes. The target asserts C/D and deasserts MSG and I/O.
Status phase
Allows the initiator to read the target‘s status information. The target asserts C/D and I/O and
deasserts MSG.
Data out phase
Allows data to be transferred from initiator to target. The target deasserts par MSG, C/D and
I/O.
Data in phase
Allows data to be transferred from target in initiator. The target asserts I/O and deasserts
MSG and C/D.
Message out phase
Not used by the system - available for future expansion.
Message in phase
Allows the target to send a message byte to notify completion of a command.
4.4 The reset condition
The reset condition is caused by the assertion of RST, and immediately clears the bus and
resets the system. Regardless of the prior bus phase, the bus resets to the bus free phase. The
hard disk controller reads the drives parameters off the disc.
Reset can only occur in the E01/E20 system at power-up rime.
4.5 The 2MHz bus
The following is a description of the 2MHz expansion bus signals used by the Winchester
Disc Host Adaptor.
R/NW (read/not-write, pin 2) is the system read/write line.
NIRQ (not-IRQ, pin 8) is the interrupt request line which is open collector and asserted by a
device pulling it low. IRQ is level triggered active-low.
NEST (not-reset, pin 14) is output only active-low system reset line. It is active on power-up.