Acorn FileStore E01, Руководство по обслуживанию

Страница: 26 / 164

Chapter 4 E01 Circuit description
FileStore Service Manual 18
4.3 The RESET circuitry
A simple reset is supplied by the components IC24, D6, R9 and C6 which provides an
extended low level on the system reset line when power is applied, to allow time for the 5
Volt rail to become established and the IC2, IC3 and IC20 id reset correctly.
4.4 Battery backup
Some system variables are maintained in the CMOS RAM contained within IC2. The supply
to this RAM is produced during power down conditions by BT1. BT1 is charged by a
constant current source circuit (consisting of
Q5, D3, N, R1 and R2) during power on
conditions. IC2‘s supply is switched between the
5 Volt rail and BT1 by Dl and D5.
4.5 The central processor
The processing power of the machine is provided by a 65C102 (IC3), an enhanced CMOS
version of the 6500 series microprocessor with its own system clocks. This processor uses 8
bit architecture.
Interrupts to the processor occur when either of the inputs IRQ or NM1 are low. Interrupts
can occur from the following sources:

IRQs from the hard disc Filestore E20 port

NMIs from the floppy disc controller

NMIs from the Econet Network IRQs from the RTC

IRQs from the printer port.
Interrupts can be disabled within the RTC by writing to the interrupt enable bits in register B
(0 disables, 1 enables). Interrupts from the printer can be disabled by writing to the relevant
register within the 65C22.
4.6 Random access memory (RAM)
There are two types of RAM in the unit.
Main memory is two 4464s (IC12 and IC13), these are organised as 64K by 4 bits per device
and together provide a 64K by 8 bit map.
The second type of RAM is the CMOS RAM contained within the RTC (IC2), which is
organised as 64 by 8 bits. The first 14 bytes are used by the RTC for time, date and other
storage etc. The remaining 50 bytes are partly used by the system software for configuration
and error recording.
4.7 Read-only memory (ROM)
Two 27256 EPROMs are fitted (IC4 and IC5), organised as 32K by 8 bits per device. These
contain the operating system and file server code respectively. These two devices are only
accessed following a power up, when their contents is copied into main memory; execution is
then transferred to the copy in RAM.