Acorn FileStore E01, Руководство по обслуживанию

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Chapter 5 E01S Fault finding
FileStore Service Manual 68
During refresh control (i.e. when an op-code fetch occurs from RAM) the processor is
reading hence pin 10 IC21 is always high. For further control of pin 10 IC21 see Memory
read/write below.
The RAS signal is generated from φ4. The purpose of the resistor capacitor network R17, C9
and R18, C8 is to alter the rise and fall times (i.e. stretch ) of φ4, hence producing RAS.
Refresh utilises the CAS before RAS refresh cycle of the 4464 DRAM which allows the CAS
signal to be held high while the RAS signal continues to cycle. Within the 4464 DRAM is a
counter for strobing the individual internal addresses of The DRAM.

RAS occurs every 500ns.

The LS57 counts 30 cycles then holds the processor.

Consequently, a refresh cycles occurs every 500ns x 30 = l5us.

The DRAM requires 256 cycles in 4rns l5us x 256 = 3.84ms
4.4.2 Memory read / write
IC9 and 10 are 64k by 4 bit DRAMs with an access time of 120ms. Together they provide
64k bytes of memory. The RAS signal is generated from φ4 by utilising IC20 as an inverter.
The CAS signal comes from φ2 and is factored with the output of IC22 pin 10. During RAM
accesses pin 8 of IC6 (the ROM enable latch) will be low, causing pin 9 of IC6 to disable the
ROM from the memory map. Due to pin 8 IC6 being low, the output of IC21 pin 3 will be
high. IC3 decodes page &FC the IO page which is not allocated within the DRAM, hence
during the DRAM read/ writes pin 8 IC3 will be high (not page &FC) therefore making pin
10 IC21 high. Due to pin 10 IC21 being high the CAS signal will always be the inverse of φ2.
The row and column addresses are strobed into the DRAM by use of IC2 and IC8. The
DRAM internal row address is strobed in on the falling edge of /RAS with A0-7 on the
outputs of IC2 and IC8. The row address being on the bus after /RAS goes low for a time
caused by the propagation delay of IC18, IC5, IC2 and IC8. The DRAM internal column
address is strobed into the DRAM on the falling edge of /CAS with A8-15 on the outputs of
IC2 and IC8.
For read operations the data is read from the DRAM on the rising edge of /CAS with the
DRAM output enable low and the processor R/W high. The output enable is controlled from
IC12 pin 7. Pin 1 IC12 will be enabled (low) when either φ2 or φ4, or both, are high. To
provide the correct input for pin 7 to go low the processor R/W needs to be high, (read) along
with pin 11 IC12. Pin 11 IC12 will be high, provided the read is not if page &FC, which is
decoded by IC3 and IC17. See Fig 4 for details.
For write operations, the data is written to the DRAM on the falling edge of the /CAS signal
with the DRAM output enable high and the processor R/W low. The DRAM output enable
will always be high due to the processor R/W line preventing pin 7 IC12 from going low. See
Fig 5 for details.
4.4.3 ROM CONTROL
A 27512 EPROM is fitted as IC7, organised as a 64k by 8bit device. It contains the operating
system and the fileserver code. This device is only accessed following a power-up, when its
contents are copied into main memory. Execution is then transferred to the copy in RAM.
On power-up C13 is charged from the supply rail via R45 and D7. As power is first applied,
the JK latch IC6 is cleared and the EPROM IC7 is enabled. The processor is reset and hence
jumps to vector &FFFC and &FFFD. The contents of the EPROM are them copied into the
DRAM up to page &FC. When address &FC is encountered, the output of IC3 pin 8 will go
low, causing IC17 to be enabled. At address &FC08 pin 10 IC12 will go low, which in turn
will cause pin 11 IC13 to go low. The result of pin 11 going low will cause a negative edge to
clock IC6 pin 9 high and disable the EPROM. The output enable of the EPROM is controlled
by pin 7 IC13, which decoded a read to memory locations outside page &FC. Data is