Acorn FileStore E01, Руководство по обслуживанию

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Chapter 4 E01 Circuit description
FileStore Service Manual 17
4. E01 Circuit description
Read this chapter in conjunction with the circuit diagrams for FileStore E01, in Appendix B
at the back of this manual.
4.1 Timing
The master system clock is 8MHz, generated by IC3 together with X2, C4, C5, and R11. This
is internally divided down by four to produce the 2MHz phase related timing clocks 02 and
04, output on pins 39 and 3 of IC3 respectively.
4.2 Sequential circuits
There are four sequential circuits in FileStore:

RAM refresh

ROM/RAM latch

Inton/intoff

Econet clock
These are described below.
4.2.1 RAM refresh
RAM Access and Refresh are handled by IC6, IC31, IC34, IC7 and IC32.
In Normal Access, RAS pulse is off at 04 and CAS is low on the rising edge at 02.
Refresh is generated by a CAS before RAS, using the internal counters in the 4464 RAM
chips. IC6 divides 02 by 60. On the next instruction fetch (synch), the processor wait state
and CAS low are asserted.
The RAS is pulsed, then after one more cycle CAS is restored and the wait state is released.
4.2.2 ROM/RAM latch
This is performed by IC7, IC31, IC34 and IC35. In its initial state, all reads are made from
ROM and all writes are made to RAM.
4.2.3 INTON/INTOFF
Non-maskable interrupts (NMIs) are performed by IC17, IC30 and IC35. Disable is at FC24
and enable at FC28. Econet network NMI is normally enabled, but is disabled during disc
access.
4.2.4 Econet clock generation
IC16, IC28 and IC26 generate the Econet clock signal with selectable speed and mark
space
ratio
. Links 3 and 4 select lµs or 2µs clock rates, derived from 0.5µs 02. IC28 is
a pre-loadable counter, links 5, 6 and 7 selecting loaded
count 1, 2 and
4. The optimum
setting is 200kHz. 1µs loaded count
=
4. IC26 is the clock transmitter, enabled
by CB2
on IC21.