Acorn FileStore E01, Руководство по обслуживанию

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Chapter 4 E20 Circuit description
FileStore Service Manual 44
The low order address lines A0 to A7 are buffered through IC5.
IC6, a 3 to 8 line decoder with three enable inputs, decodes the low order addresses &40 to &43, i.e
output pin 15 goes low when the low order address is &40, &41, &42 or &43.
IC7 is another 3 to 8 line decoder which takes the output from IC6 and CNPGFC and 2MhzE as
enable inputs. The 2 least significant address bits A0 and Al are decoded along with R/NW into the
required 5 separate signals shown above.
(1)
Y0 (pin 15) Is read data (R/NW = 1)
(2) Y4 (pin 11) is write data (R/NW = 0)
(3) Y1 (pin 14) is status
(4) Y6 (pin 9) is select
(5) Y7 (pin 7) is enable IRQ
All these outputs are active-low.
When either
of the two data transfer paths is selected (Y0 or Y4) an ACK signal is generated by
clocking a D-type flip-flop (half of IC1l). This flip-flop is cleared direct from the REQ line, and
thus the REQ/ACK handshake is facilitated.
The other half of IC1l facilitates the SEL/BSY handshake. The D-type is clocked by Y6 to generate
select and is cleared by BSY.
When Y7 is selected, the least significant bit on the data bus (D0) is clocked into a D-type flip-flop
(half of
IC 10). If this value is a 1 then the latch (2 NANDs of IC12) is enabled and an IRQ will be
generated at the next failing edge of REQ. To disable interrupts Y 7 is selected with ad on D0. IR Qs
are enabled only for a very short time (around l0ms) when ensuring a sequential file buffer.
4.6.2 Buffering
The data bus (D0 to D7 of host system, DB0 to DB7 of SCSI interface) is buffered in the write
direction by an octal 3-state buffer IC1 and an octal transparent latch (IC2). IC2 is enabled by Y4 of
IC7 which is the write data signal. Because IC2 is a transparent latch,
data will remain valid on the
output side when the enable is deasserted. The outputs from IC2 are gated through 8 open collector
NAND buffers which are enabled from the I/O control line of the SCSI interface and which invert
the bus signals. To write data across the Host Adapter requires that both R/NW = 0 and I/O = 1.
The data bus is buffered and inverted in the read direction by an octal 3-state inverting buffer which
is enabled by Y0 of IC7 which is the read data signal, see previous subsection.
The control signals need by the SCSI interface are available for rending by the host system. They
can be latched onto IC4, an octal transparent latch, which when it is enabled by Y1 of IC7. The
control signals appear on the data bus as shown in the following table:
D0
MSG
D1 BSY
D2 0
D3 0
D4 NIRQ (see 11.6.1)
D5 REQ
D6 I/O
D7 C/D
All these control signals are inverted either by IC15 or IC9 prior to being latched, so all values read
from the data bus are active high.