Acorn Computers Limited BBC A, Руководство по оборудованию, Страница: 40 / 47

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3.21 Double Accessing.
It is possible for a peripheral device, which is attached to the 1MHz bus, to be accessed twice by the
CPU. This happens as a result of the way in which the pulse stretching circuitry within the microcomputer
works. Basically, it occurs because the CPU clock is in fact held high until the falling edges of the 1MHz
clock and the 2 MHz clock are coincident. If a 1MHz peripheral is accessed when the 1MHz clock is high
then this peripheral will be given almost immediate access to the CPU. However, because of the fact that
the CPU clock is held high, waiting for the coincident edge, the peripheral device will be accessed for a
second time when the 1MHz clock next goes high. This characteristic will not normally be a problem
unless the peripheral is reading or writing to a device in order to change the state of an interrupt flag, for
instance. This could result in an interrupt going unrecognised.
3.22 NPGFD (JIM).
The NPGFD signal is very similar to the NPGFC line the only difference being that this line is active when
the address bus holds a valid address in the range &FD00 to &FDFF. As with FRED this signal also
suffers from glitches and must, therefore, be cleaned up using a similar clean up circuit to one of those
shown in figure 3.5.
The NPGFD line is intended to be used in conjunction with the paging register in FRED (address &FCFF)
to allow the machine to address up to 64k of additional memory. This memory would normally be
accessed one page (256 bytes) at a time, the paging register in FRED (at address &FCFF) would contain
the page number i.e. up to 256 pages each with 256 bytes. The value contained in the paging register is
referred to as the "Extended Page Number" (EPN)
Acorn Computers Ltd. have adopted a convention for use of the extended pages which presently is as
follows;
EPN' 5. Allocation.
0 to &7F Reserved for use by Acorn.
&80 to &FF General user applications.
TABLE 3.3
On power up or hard break the contents of the paging register are set to 0.