Acorn Computers Limited BBC A, Руководство по оборудованию, Страница: 28 / 47

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inverted inputs on the Acorn circuit diagram), is taken low. This results in the output from the NAND gate
going to logic '1', which is used to inform the cycle stretch circuitry that a slow access device requires
service. The logic '1' is first inverted by part of IC33 (74LS04) before being fed to the set input of a
bistable (half of IC31) and also one input of a NOR gate (part of IC~9). This bistable remains set, thus it
effectively "remembers" that a slow access has been requested.
The output of the bistable is fed via the NOR gate to the input of another bistable, part of IC34. This
second bistable is used to reset the "memory" bistable after a time governed by the phase relationship
between the 1MHZ and 2MHz clock signals. Meanwhile, one of the 2MHz clock cycles will have been
masked off by this second bistable. Depending on the phase relationship between the two clocks at the
time of the request, the 2MHz clock to the microprocessor will be held at logic '1' for either 3 or 5 half
cycles.
3.9 The "Econet" Circuitry.
The heart of the "Econet" circuitry is IC89, a Motorola MC6854 Advanced Data Link Controller (ADLC)
Connection to the "Econet" network is by a 5-pin l80 degree DIN socket (SK7) on the rear of the machine.
The network clock I] connects to pins 3 and 5 of this socket, whilst pins 1 and 4 carry the data. Pin 2
is connected to 0 volts. The data line is bi-directional, thus both transmitted and received data is carried
along the same pair of wires in half-duplex mode. Unlike the RS423 serial data transmission port, the
"Econet" system uses a differential mode of operation to provide high common mode noise immunity and
achieve high transfer rates.
Pin 6 (TXD) of the ADLC feeds the TTL data to be transmitted to one half of a differential line driver
(IC93). provided that this line driver is enabled by the output of IC91, one quarter of which is used as an
inverting buffer, data will then be transmitted. The input signal to this inverter comes directly from pin 2
(RTS) of the ADLC.
Any "incoming" data on the data lines is converted to a TTL signal by an analogue comparator (one half
of IC94). The TTL signal is then fed into the received data input (RXD) of the ADLC. In a similar way, the
network clock is also detected by the other half of IC94. The output of this comparator feeds both the
receive clock and transmit clock inputs of the ADLC. Thus it is not possible to use different receive and
transmit baud rates.
The network clock must always be present in order for the ADLC to synchronise correctly, a monostable
(half of IC87) is used to achieve this. The time constant of this monostable is such that as long as the
clock signal is present it remains permanently triggered. One output of the monostable provides