Acorn Computers Limited BBC A, Руководство по оборудованию, Страница: 29 / 47

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the data carrier detect signal (DCD) into the ADLC, the other output activates the clear to send signal
(CTS) via a dual input NAND Schmitt gate. By using this technique, network activity is suspended if the
clock signal is interrupted.
Because of the democratic nature of the Econet system it is possible for two or more devices to attempt
simultaneously to transmit data on the network. This condition is known as a "collision". A collision on the
network will cause the nominal signal level on the data lines to drop because of the increased he loading,
this condition is detected by a dual comparator (IC95). The dual comparator arrangement sends a TTL
output signal into one quarter of IC91, which is acting as an inverter. The output of this inverter activates
the clear to send input of the ADL.C via another quarter of IC91, thus transmission is suspended in the
event of a collision. Each of the microcomputers involved in the collision will then retry. The condition is
detected by both machines and an arbitration algorithm within the "Econet" system software ensures that
no two computers will retry simultaneously.
The individual station address is set by the group of links S11, in conjunction with IC96. This is detailed in
the chapter 4 which deals with link functions. The "Econet" network must be terminated at each end with
its characteristic impedance to prevent signal reflections. On early issue printed circuit boards resistors
R26,42,53,54,56, capacitors C19,22 and diode D3 provide this optional termination.
The network clock is usually derived from an external "clock box", however, on some early issue main
PCB's, circuitry was provided to enable the network clock to be generated on board. This circuitry
consisted of IC90 (40l8), IC97 (74LS74) and the normally unused half of IC93. The 6MHz clock signal
derived from the output of IC37 is divided by two, using half of IC97 (74LS74). This 3MHz signal is then
further subdivided in to a range of frequencies by IC90, link S3 is then used to select the required
base clock frequency. Clock base frequencies usually lie in the region 75KHz to 625KHz. The required
frequency is dependent on the line length of the network. The base clock frequency is then fed directly in
to the input the normally unused half of the line driver IC93. The of this line driver is then connected to the
clock output the DIN "Econet" connector and provides the network clock source.
The link S5 is used to enable the clock line driver and link S6 may be used to further subdivide the clock
base frequency by 2 or 4.