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3.12 The Floppy Disc Interface.
The BBC Microcomputer was designed for use with either one or two 5 1/4 inch or 8 inch floppy disc drive
units. These drives may be single or double sided.
In order to use floppy disc drives with the BBC Microcomputer, the disc interface circuitry must be fitted to
the main PCB of the machine (see chapter 6). The heart of the floppy disc interface is an Intel P8271
Floppy Disc Controller (FDC) chip (IC78). This device controls data exchange between the floppy disc
drive unit and the data bus of the microcomputer. An interrupt generated by the FDC acts on the non-
maskable interrupt (NMI) line of the microprocessor (IC1). Note that apart from the FDC, there are two
other devices within the microcomputer which generate NMI signals. These are the "Econet" interface
and some 1MHz bus peripherals.
The TTL output signals from the FDC are fed into open collector NAND buffers, type 7438 (IC79 and
IC8~). The outputs from these buffers connect to the disc drive unit via the disc interface plug (PL8). The
data input (Read Data) and index pulse (Index) signals from the floppy disc drive enter the microcomputer
on pin 30 and pin 4 (5 ¼ inch drive) respectively. In the case of an 8-inch drive, the index pulses enter on
pin 8 of this connector. The option of whether the index pulse input to the P8271 FDC is taken from pin 4
(5 1/4-inch drive) or pin 8 (8 inch drive) of the connector is selected by a PCB link (S10)
The unseparated data signal from the floppy disc drive is fed into one half of a 74LS123 monostable
(IC87), which "stretches” the incoming pulses to a length determined by the time constant of R33 and
C13. The outputs of this monostable then feed into a data separation circuit consisting of a dual four-bit
binary counter (IC81) and a triple 3-input NAND gate (IC82). This arrangement produces the “data
window" signal which is fed to pin 26 of the FDC. The negated output of IC87 also supplies the read data
input to the FDC.
Link S27 is used to route either the 8MHz (5 ¼ inch drive) or the 16MHz clock signal (8 inch drive) from
the video ULA into one input of a 74LS393 dual 4-bit binary counter (IC86). The divide by four (QB)
output of this counter provides the clock input to the FDC. Thus either a 2MHz or 4MHz FDC clock is
provided, depending on which drive size is to be used. The remaining half of IC86 further sub-divides the
FDC clock to produce either a 31.25KHz or 62.5KHz signal. This signal is then used in conjunction with
IC83, IC84 and IC85 to detect the drive index pulses and to determine when the drive is ready for a read
or write operation.