Abit AB-CX6, Руководство пользователя

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1-4 Chapter1
CX6
DRAM synchronization has set the stage for system designers to move from a 66MHz to a
100 MHz system bus, partially closing the speed gap between processor and memory. But
even as engineering teams wrestle with this design challenge, microprocessors are
advancing to speeds of 300MHz, 400MHz, and beyond.
Memory technologists are now developing new DRAM architectures that are expected to be
fast enough to unleash the power of tomorrow's processors. These architectures add special
registers to each DRAM pin and special controller functions to the DRAM array core.
Currently, the most fully developed of these architectures is Direct Rambus DRAM (Direct
RDRAM) which uses a special controller, layout, and bus to achieve high I/O bandwidth.
While other firms were employing techniques such as SRAM caches, parallel arrays of
DRAMs, and expensive frame buffers to increase memory bandwidth, Rambus, Inc. took an
entirely different tack. Rambus targeted a two-byte wide data path, 800MHz transfer rate,
and a 95% protocol efficiency. The development resulted in a new chip-to-chip bus, termed
the Direct Rambus Channel (DRC) which includes a controller and one or more Direct
RDRAMs connected together via a common bus. Using a limited number of high-speed
signals to carry all address, data, and control information, DRC links main memory to
system devices that have a need to access memory, including microprocessors, DSPs,
graphics processors, and ASICs. Low voltage swing signaling is used with conventional
PCB technology to permit data transfer up to 800Mbits/s/pin, resulting in the 1.6GB/s peak
bandwidth that will be required for Intel's projected 1999 high-end systems.
Table 1-1 Direct Rambus Technology Features
Frequency 800 MHz
Maximum Device Bandwidth
1.6 Gbytes/sec
Data Width 16 or 18 bits
Protocol Efficiency for 32-byte Transfers
95-100%
Voltage 2.5/1.8V
STR (Suspend to RAM)
The CX6 supports the STR function. The STR function enables a PC to achieve the S3 state
during idle periods, then quick “wake up” and retrieve the last “state” of the system before it
went to sleep. When idle, STR-enabled systems consume only a small fraction of the power
used for full operation. Instead of shutting down the system to save power when not in use
and then having to reboot later, users can let the STR function take over and not have to
worry about using power to run all the electronics, fans and disks. When needed, a PC with
STR function can restore all applications and features to an operational state within a few
seconds.