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21
Figure 9 Core part of ZLAN3003S Schematic Diagram
1) Pins extract for 3003S: CTS, LINK, 485_TEN, RTS, nRST, TXD, RXD and DEF.
All these pins are directly extracted from the 1003 chip.
2) The power input can be 5V or 3.3V. From the power supply circuit, 5V input was
reduced to 3.3V through 1117-3.3 chip, and 3.3v to 1.8v through 1117-1.8. It
should note that if the voltage is 9V, 12V, 24V and so on, please use the power
plan of SNMP card instead of the LDO chip of 1117. Because of the dual power
supply in this design, 1.8V is generated externally, so the VCC33I and VCC18O
of the chip both connect with 1.8V power supply.
3) Since the high speed UART is not used here, pull up the CONFIG pin, and let
RXD2 and TXD2 hang on.
4) It is important to note that RSH1 and RSL2 can only be welded one when
1
2
3
4
5
6
7
J 3
C ON 7
V CC 5 0
V CC 3 3
G ND
n R ST
TX D
R XD
D EF
4
3
2
1
J 4
C ON 4
LIN K
4 8 5 _ T EN
C TS
R TS
C 0 3
0 . 1 u
V CC 3 3
C 0 2
TA J B 4 7 6 K1 0 1 R N J
V CC 5 0
R 2 0 3
0
R 2 0 1
4 . 7 K
D 9 2
R UN _ L ED
A
D
J
1
V IN
3
V OU T
2
U 3
LM 1 1 1 7 -3 .3
A
D
J
1
V IN
3
V OU T
2
U 4
LM 1 1 1 7 -1 .8
V CC 1 8
C 0 4
TA J B 4 7 6 K1 0 1 R N J
C 0 1
0 . 1 u
Z
L
S
N
3
0
0
3
S
o
u
t
p
u
t/
in
p
u
t
p
in
s
R
U
N
_
L
ED
VC
C
1
8
C
T
S
CTS
n
R
ST
VCC18
VCC33
TXD
R
U
N
_L
E
D
PULL_UP1
RXD
RTS
CONFIG
SPEED
PULL_DOWN5
PULL_DOWN4
SPEED
PULL_UP2
PULL_DOWN1
PULL_DOWN2
PULL_DOWN3
SPEED
CONFIG
N
ET
_
R
X+
N
ET
_
R
X-
N
ET
_
T
X+
N
ET
_
T
X-
L
IN
K
AC
T
D
EF
4
8
5
_
EN
PULL_UP2
PULL_UP1
RP
10K
R2
1M
R1
12.1k
C1
33p
V
CC
4
R
E
SE
T
2
MR
3
G
N
D
1
U1
max811reus
1 0 0 M _ L IN K
6 1
R TS
6 2
G ND
6 3
PU LL _ U P
6 4
R XD 0
6 5
V CC 1 8
6 6
TX D 0
6 7
R XD 1
6 8
V CC 3 3
7 6
V CC 1 8
7 5
n R ST
7 4
C TS2
7 3
SD A
7 2
SC L
7 1
N C
7 0
TX D 1
6 9
N C
8 0
N C
7 9
G ND
7 8
N C
7 7
NC
1
NC
2
NC
3
V
CC
18
4
NC
5
NC
6
NC
7
NC
8
R
X
D
2
9
T
X
D
2
10
NC
11
NC
12
V
CC
33
13
R
U
N
_L
E
D
14
V
CC
18
15
C
T
S
16
G
N
D
17
NC
18
NC
19
NC
20
G ND
4 0
X TL+
3 9
X TL-
3 8
V CC 1 8
3 7
V C1 8
3 6
V CC 3 3
3 5
G ND
3 4
C ON FIG
3 3
SP D1
3 2
PU LL _ D OW N
3 1
TE ST_ DO W N
3 0
V CC 3 3
2 9
PU LL -D O W N
2 8
PU LL _ D OW N
2 7
SP D0
2 6
PU LL _ U P
2 5
PU LL _ D OW N
2 4
V CC 1 8
2 3
N C
2 2
N C
2 1
485_T
60
V
CC
33
59
NC
58
NC
57
V
CC
18
56
D
E
F
55
A
CT
54
L
IN
K
53
V
CC
18
O
52
V
CC
33
I
51
G
N
D
50
G
N
D
49
T
X
-
48
T
X
+
47
V
CC
18
46
R
X
-
45
R
X
+
44
G
N
D
43
V
CC
33
42
B
G
_R
E
S
41
U2
ZLAN1003
X1
25M
RSL1
10K
R5
4.7K
C2
33p
R4
4.7K
RSL2
10K
R3
10K
RSH1
10K
V CC 1 8
V CC 3 3
V CC 1 8
V CC 1 8
V CC 3 3
V CC 1 8
V CC 3 3
V CC 3 3
V CC 3 3
V CC 1 8
V CC 3 3
V CC 3 3
V CC 3 3
V CC 1 8
V CC 1 8
S e l e c t : R S L 2 t o u s e l o w s p e e d
V CC 1 8
S e l e c t : R S H 1 t o u s e h i g h s p e e d