6. DMA Controller
67
REGISTER:
ADDRESS:
AT ADDRESS:
ACCESS:
D7
D6
D5
D4
D3
D2
D1
D0
---
W/O, D0 specifies channel
1= Bits D6 and D4 affect channel 1
0= Bits D6 and D4 affect channel 0
Reserved
DMABSR
0F018h
DMA bus size register
Reserved
1
1
1
1
1
1= Channel target bus width is 16 bits
0= Channel target bus with is 8 bits
Reserved
1= Channel requestor bus width is 16 bits
0= Channel requestor bus width is 8 bits
Reserved
DMA Bus Size Register
DMA Chaining Register
The DMACHR register is used to enable and disable the chaining buffer-transfer mode
for a selected channel. The following steps describe how to set up a channel to perform
chaining buffers transfers.
1. Set up the chaining interrupt (DMAINT) service routine.
2. Configure the channel for single buffer-transfer mode.
3. Program the mode registers.
4. Program the target address, requestor address, and byte count registers.
5. Enable the channel for the chaining buffer-transfer mode. This activates the chaining
status signal.
6. Enable the DMAINT interrupt and service it. The service routine should load the
transfer information for the next buffer transfer.
7. Enable the channel.
REGISTER:
ADDRESS:
AT ADDRESS:
ACCESS:
D7
D6
D5
D4
D3
D2
D1
D0
---
W/O, D0 specifies channel
1= Bit D2 affects channel 1
0= Bit D2 affects channel 0
1= Enable chaining buffer transfer mode for the channel specified by D0
0= Disable chaining buffer transfer mode for the channel specified by D0
Reserved
DMACHR
0F019h
DMA chaining register
Reserved
1
0
0
Reserved
DMA Chaining Register
