5. Counter/Timers
41
PROGRAMMABLE REGISTERS
The counter/timers are accessed through four I/O addresses as shown in the following
table. Each counter/timer occupies an I/O port address through which the preset count
values are written and both the count and status information is read. The Control
register occupies the remaining I/O port address, which services all three
counter/timers.
Counter/Timer Register Addressing
Address
Register
Operation
0040h
Channel 0 Count
Read/Write
0040h
Channel 0 Status
Read
0041h
Channel 1 Count
Read/Write
0041h
Channel 1 Status
Read
0042h
Channel 2 Count
Read/Write
0042h
Channel 2 Status
Read
0043h
Control
Write
Count Registers and Count Latch
Each counter/timer has a 16-bit Count register and count latch. Data is transferred to
the counter/timers through the Count register and from the counter/timers through the
count latch. The Control register defines the method for accessing the 16-bit Count
register through an 8-bit I/O port.
7
6
5
4
3
2
1
0
High Byte
Register: Count High
Address: 40h + Channel
Access: Read and Write
Count Register High Byte
Low Byte
7
6
5
4
3
2
1
0
Register: Count Low
Address: 40h + Channel
Access: Read and Write
Count Register Low Byte
