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4. INTERRUPT CONTROLLER
The ZT 8904 includes two Intel-compatible 8259 cascaded interrupt controllers that
provide a programmable interface between interrupt-generating peripherals and the
CPU. The interrupt controllers monitor 15 interrupts with programmable priority. When
peripherals request service, the interrupt controller interrupts the CPU with a pointer to a
service routine for the highest priority device. The major features of the interrupt
architecture are listed below. The ZT 8904 does not support cascaded interrupt
controllers on the STD bus.
•
15 individually maskable interrupts
•
Level-triggered or edge-triggered recognition
•
Fixed or rotating priorities
The interrupt architecture is illustrated in the "
Interrupt Architecture
" figure following.
Interrupt configuration jumpers (W17-22) are used to customize the interrupt
architecture to the needs of the application. These jumpers connect one of two interrupt
sources to an interrupt input. Wire-wrap techniques provide additional flexibility.
The interrupt sources are summarized below.
Backplane: Five STD bus interrupts are routed to the interrupt configuration jumpers.
These interrupts are INTRQ*, INTRQ1*, INTRQ2*, INTRQ3*, and INTRQ4*.
All five interrupts are supported in an STD 32 backplane. These interrupts
are active-low on the STD bus and inverted before they reach the interrupt
configuration jumpers.
Frontplane:Three frontplane interrupts are routed to the configuration jumpers. These
interrupts are available through connector J2 as active-low inputs that are
inverted before reaching the interrupt configuration jumpers. The pin
assignments for connector J2 are given in Appendix B, "
Specifications
."
Many STD bus boards include a J2-compatible connector for routing
interrupts to the ZT 8904 through a ribbon cable. This architecture is useful if
the application requires more interrupts than are available on the STD bus.
Local:
Local interrupt sources include the keyboard controller, serial ports (COM1,
COM2, COM3, and COM4), multiprocessor communications, 1284 parallel
port, event sense parallel I/O, real-time clock, timer/counters, DMA
controller, Math coprocessor, watchdog timer, and optional IDE controller.
PROGRAMMABLE REGISTERS
Each interrupt controller includes four initialization registers, three control registers, and
three status registers. The I/O port addressing for the interrupt controllers is given in the
