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6. DMA CONTROLLER
The DMA controller used on the ZT
8904 is contained within the 386
EX
microprocessor. It improves system operation by allowing external or internal
peripherals to directly transfer data to or from ZT 8904 memory. The DMA controller can
transfer data between memory and I/O with 8-bit or 16-bit data path widths. It has
features that are not available on an 8237A, and it can be configured to operate in an
8237A-compatible mode.
The DMA controller contains two identical, independently configurable channels. One of
the following peripherals can request DMA service:
•
A 386 EX external peripheral (connected to the DRQ0 or DRQ1 pins)
•
A 386 EX internal peripheral (asynchronous serial I/O, synchronous serial I/O, or
counter/timer unit)
The DMA configuration register (DMACFG) is used to select one of the possible
sources. In addition to these hardware request sources, each channel contains a
software request register that can be used to initiate transfers. Both channels share a
common end-of-process signal. The major features of the DMA architecture are listed
below.
•
One STD bus/local DMA channel (Channel 0)
•
One local DMA channel (Channel 1)
•
STD bus DMA slave support
•
Buffer transfer processes:
–
Single buffers
–
Autoinitialized buffers
–
Chained buffers
•
Buffer transfer modes supported:
–
Single mode
–
Block mode
–
Demand mode
•
DMA transfers over the full local memory range
INTEL 386 EX INTERNAL ARCHITECTURE
The 386 EX DMA controller internal architecture is illustrated in the "
386 EX Internal
DMA Controller Connections
" figure following. This figure details all of the DRQ source
