Ziatech Corporation ZT 8903 Hardware User Manual Download Page 73

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7. Real-Time Clock

Register B

Address: 0Bh
Access: Read and Write

SET

PIE

AIE

UIE

24/12 DSE

Daylight Savings

0 Disabled
1 Enabled

24-hour/12-hour Operation

0 12-hour mode
1 24-hour mode

Data Mode

0 BCD
1 Binary

Update-End Interrupt

0 Disabled

1 Enabled

Alarm Interrupt Enable

0 Disabled
1 Enabled

Periodic Interrupt Enable

0 Disabled

1 Enabled

Cycle Update

0 Real Time
1 Latch Time

Register C

Address: 0Ch
Access: Read

IRQF

Update Flag

0 No update

1 Update

Alarm Flag

0 No alarm

1 Alarm

Periodic Interrupt Flag

0 No interrupt
1 Interrupt

Interrupt Pending

0 No interrupt

1 Interrupt

Summary of Contents for ZT 8903

Page 1: ...ZT 89CT04 Single Board 386 EX Computer ZT 8904 ZT 8903 Hardware User Manual...

Page 2: ...EAL TIME CLOCK 15 KEYBOARD CONTROLLER 16 AC POWER FAIL PROTECTION 16 2 GETTING STARTED 17 UNPACKING 17 SYSTEM REQUIREMENTS 17 MEMORY CONFIGURATION 17 SYSTEM RAM 16 BIT PSEUDO STATIC RAM 17 I O CONFIGU...

Page 3: ...ONNECTIONS AND MASK 53 CHANNEL 0 REQUESTOR ADDRESS REGISTERS 53 CHANNEL 1 REQUESTOR ADDRESS REGISTERS 55 CHANNEL 0 TARGET ADDRESS REGISTERS 56 CHANNEL 1 TARGET ADDRESS REGISTERS 58 CHANNEL 0 BYTE COUN...

Page 4: ...89 16C50A ENHANCED OPERATING MODE 90 11 SYSTEM REGISTERS 96 PROGRAMMABLE REGISTERS 96 ADDITIONAL INFORMATION 98 12 WATCHDOG TIMER 99 WATCHDOG TIMER OPERATION 99 PROGRAMMABLE REGISTERS 100 WATCHDOG TI...

Page 5: ...TEM LATCHUP 139 POWER SUPPLY SEQUENCE MISMATCH 140 SIGNAL LEVEL MISMATCH 142 PROTECTING CMOS INPUTS 143 RISE TIMES 143 INDUCTIVE COUPLING 144 ADDITIONAL INFORMATION 145 D CUSTOMER SUPPORT 146 TECHNICA...

Page 6: ...rational Read this chapter before attempting to use the board Chapter 3 STD Bus Interface discusses the STD 32 architecture and its effect on the operation of the ZT 8904 Chapter 4 Interrupt Controlle...

Page 7: ...etection as a means for giving the application advanced warning of an impending power failure Appendix A Jumper Configurations demonstrations how the ZT 8904 offers several options tailoring the opera...

Page 8: ...386 EX TM Integrated IDE Subsystem STD 32 and STD compatible Local Bus Video Option AC DC Power Fail Detection Push button reset 24 points of Digital I O 4 serial ports 1 parallel port 2 RS 232 2 RS 2...

Page 9: ...available on the ZT 8903 ZT 8904 supports a multiprocessing option not available on the ZT 8903 ZT 8904 includes RS 485 support not available on the ZT 8903 ZT 8904 includes four serial ports and the...

Page 10: ...s include Two RS 232 serial channels Two RS 232 485 DMA capable serial channels not supported by ZT 8903 IEEE 1284 parallel port Centronics ECP EPP Optional IDE disk drive not supported by ZT 8903 24...

Page 11: ...ng instructions STAR BIOS is the DOS platform operating on more than one master in a single STD bus system Each master supports the Ziatech Industrial BIOS operating environment and is capable of shar...

Page 12: ...space and a 64 Kbyte I O address space 24 Point Digital I O Interrupt Inputs Two RS 232 and Two RS 232 485 Serial Ports Centronics Port ECP EPP AC DC Power Detect ZT 8904 25MHz 386 EX CPU Bus Interfac...

Page 13: ...iatech Industrial BIOS architecture is shown in the I O Address Map Local Bus Video The ZT 8904 supports both STD bus and local bus video adapters For STD bus video Ziatech offers video boards that su...

Page 14: ...I O The ZT 8904 includes three 8 bit parallel I O ports for a total of 24 parallel I O lines Each line is programmable as an input or an output with readback The outputs sink 12 mA and do not glitch d...

Page 15: ...annel 0 supports the local 1284 parallel port or combines with DMA channel 1 to support one of the local serial ports See Chapter 6 DMA Controller for more information Watchdog Timer The two stage wat...

Page 16: ...he addition of an AC transformer connected to connector J3 the ZT 8904 monitors AC power to permit an orderly shutdown during a power failure When AC power falls below an acceptable operating range a...

Page 17: ...order to handle the boards SYSTEM REQUIREMENTS The ZT 8904 is designed for use with or without an STD bus backplane The ZT 8904 is electrically mechanically and functionally compatible with the STD 32...

Page 18: ...ined by zero wait state STD 32 specifications During local memory operations the STD bus is held static to decrease system electrical noise and power consumption The ZT 8904 supports 128 Kbyte battery...

Page 19: ...cture is shown in the I O Address Map figure following STD bus expansion I O is transferred at a rate of up to 1 Mbyte second for 8 bit data and 1 5 Mbytes second for 16 bit data The ZT 8904 supports...

Page 20: ...CONFIGURATION AVAILABLE CPU CONFIGURATION WATCHDOG CPU CONFIGURATION AVAILABLE COM1 IDE RESERVED AVAILABLE COM2 RESERVED COM4 COM3 RESERVED PRINTER IEEE 1284 RESERVED CPU CONFIGURATION RESERVED AVAIL...

Page 21: ...The following topics present a brief introduction to the setup and configuration of the ZT 8904 For documentation specific to the BIOS and other utilities see the Ziatech Industrial BIOS manual shipp...

Page 22: ...arameters in the SETUP screen are easily changed Use the arrow keys to select a parameter then press or to step through the valid choices for that parameter A dynamic help line at the bottom of the sc...

Page 23: ...ort for multiple bus master operation STD 32 Operation Data transfers between the ZT 8904 and any STD bus memory or I O board occur eight bits at a time for boards supporting an 8 bit data bus and 16...

Page 24: ...INTRQ3 and INTRQ4 These interrupts are input from the STD bus and connected to the interrupt controller through a jumper configuration block for increased flexibility SDMABP Supports Standard Archite...

Page 25: ...a single vector for each input it is up to the application software to poll each possible source on the shared interrupt request signal to determine which is requesting service This procedure is fine...

Page 26: ...oller as shown in the STD Bus Vectored Interrupt Structure figure following ZT 8904 STD BUS INTRQ INTRQ INTRQ1 INTRQ2 INTRQ INTRQ INTRQ1 INTRQ2 INTERRUPT SOURCE 7 INTERRUPT SOURCE 3 INTERRUPT SOURCE 2...

Page 27: ...master operation through the installation and removal of resistor packs RP16 and RP17 With both resistor packs installed the ZT 8904 functions as a permanent master With both resistor packs removed th...

Page 28: ...ntelligent I O board operates at full speed when communicating with local memory local I O and dual port RAM The ZT 8904 also operates at full STD bus speeds when accessing the dual port RAM It is not...

Page 29: ...elligent I O system is lower system cost The intelligent I O architecture operates in STD 32 bus structures Dual port RAM arbitration is local to each intelligent I O board eliminating the need for a...

Page 30: ...nal PBRESET P48 In response to any of these signals the ZT 8904 initializes local peripherals and activates the STD bus system reset SYSRESET P47 In a multiple master system a ZT 8904 configured as a...

Page 31: ...routed to the interrupt configuration jumpers These interrupts are INTRQ INTRQ1 INTRQ2 INTRQ3 and INTRQ4 All five interrupts are supported in an STD 32 backplane These interrupts are active low on the...

Page 32: ...errupt controller is 20h and the base address of the slave interrupt controller is A0h Interrupt Controller Register Addressing Address Register Operation Base 0h IRR ISR IPR Read Base 0h ICW1 Write B...

Page 33: ...10 1284 PARALLEL J2 PIN 8 STD BUS INTRQ2 J2 PIN 6 STD BUS INTRQ4 MULTIPROCESSING SERIAL PORT COM1 SERIAL PORT COM2 KEYBOARD CONTROLLER STD BUS INTRQ1 TIMER COUNTER 0 IR14 IR13 IR12 IR11 IR10 IR9 IR8 I...

Page 34: ...Initialization Programming figure below ICW1 ICW2 and ICW3 must be programmed during each initialization sequence ICW4 may or may not be programmed as required by the application ICW1 BASE ADDRESS 0...

Page 35: ...ress Base 1 Access Write 0 0 0 0 0 1 0 0 7 6 5 4 3 2 1 0 Master Initialization Register ICW3 Register Slave ICW3 Address Base 1 Access Write 0 0 0 0 0 0 1 0 7 6 5 4 3 2 1 0 Slave Initialization Regist...

Page 36: ...Address Base 1 Interrupt mask Access Read and Write 0 Reset 1 Set Operational Register OCW1 Level Mode 7 6 5 4 3 2 1 0 Register OCW2 Address Base 0 Interrupt level Access Write 000 IR0 0 0 001 IR1 01...

Page 37: ...mmand 0 No poll 1 Poll 11 Special mask Operational Register OCW3 Status Registers IRR ISR IPR Each interrupt controller includes three status registers A status register is selected by programming the...

Page 38: ...101 IR5 110 IR6 111 IR7 Interrupt 0 No Interrupt present 1 Interrupt present IR 0 Status Register IPR ADDITIONAL INFORMATION Refer to the Ziatech Industrial Computer System Manual for more informatio...

Page 39: ...r architecture is illustrated in the Counter Timer Architecture figure below In some cases not all counter timers are available for application development In an MS DOS system for example counter time...

Page 40: ...ed high to enable counting 1 Transitions after programmed count expires Gate tied high to enable counting 2 Periodic single pulse after programmed count expires Gate tied high to enable counting 3 Squ...

Page 41: ...tus Read 0041h Channel 1 Count Read Write 0041h Channel 1 Status Read 0042h Channel 2 Count Read Write 0042h Channel 2 Status Read 0043h Control Write Count Registers and Count Latch Each counter time...

Page 42: ...Terminal count interrupt Mode 0 001 Retriggerable one shot Mode 1 010 Rate generator Mode 2 011 Square wave generator Mode 3 100 Software strobe Mode 4 101 Hardware strobe Mode 5 110 Same as 010 111 S...

Page 43: ...BCD Operating Mode 000 Terminal count interrupt 001 Retriggerable one shot 010 Rate generator 011 Square wave generator 100 Software strobe 101 Hardware strobe 110 Same as 010 111 Same as 011 Access M...

Page 44: ...h 0 Enabled 1 Disabled Control Latch 0 Enabled 1 Disabled 1 STL CT2 CT0 100 Counter 2 Multiple Latch Control Register ADDITIONAL INFORMATION Refer to the Ziatech Industrial Computer System Manual for...

Page 45: ...serial I O synchronous serial I O or counter timer unit The DMA configuration register DMACFG is used to select one of the possible sources In addition to these hardware request sources each channel c...

Page 46: ...1 supports the following devices as DRQ sources DMACFG 2 0 Local floppy disk PC87303 internal floppy controller Local IEEE 1284 PC87303 internal parallel port COM2 receive buffer full COM1 transmit bu...

Page 47: ...shared with RXD1 and TXD1 These shared functions prevent using COM 2 while DMA channel 1 is used If DMA channel 0 is used but DMA channel 1 is not COM 2 can be used but only as a 3 wire interface use...

Page 48: ...nsfers I O MAPPING The 386 EX maps the DMA controller into the standard PC AT I O locations for DMA channel 0 and channel 1 The 386 EX DMA Controller Registers table lists I O addresses of the DMA con...

Page 49: ...l byte count 1 Fly By and Two Cycle Bus Cycles There are two bus cycle options for data transfers fly by and two cycle Fly by allows data transfers to occur in one bus cycle However it requires that t...

Page 50: ...hardware reset Any bit described as Reserved should be written with a 0 unless otherwise indicated 386 EX DMA Controller Registers Register Address Expanded Address PC AT Description PINCFG 0F826h Pi...

Page 51: ...nt 8 15 DMA1BYC2 0F099h Channel 1 byte count 16 23 DMASTS 0F008h 0008h DMA status register DMACMD1 0F008h 0008h DMA command register 1 DMACMD2 0F01Ah DMA command register 2 DMAMOD1 0F00Bh 000Bh DMA mo...

Page 52: ...en with a 0 Must be written with a 0 Must be written with a 0 Must be written with a 1 Must be written with a 1 1 connect TXD1 to the package pin 0 connect DACK1 to the package pin required for DMA op...

Page 53: ...ion 000 Connect external channel 1 DRQ pin to DRQ1 001 Connect SIO channel 1 receive buffer full signal to DRQ1 010 Connect SIO channel 0 transmit buffer empty signal to DRQ1 011 Connect SSIO receive...

Page 54: ...T ADDRESS ACCESS D7 D6 D5 D4 D3 D2 D1 D0 0F011h ND ND ND ND ND ND ND ND DMA0REQ2 R W BP 0 Channel 0 requestor address bit 16 Channel 0 requestor address bit 17 Channel 0 requestor address bit 18 Chann...

Page 55: ...ress bit 7 ND ND ND ND ND ND ND ND DMA1REQ0 0F012h Channel 1 requestor address bits 0 7 Channel 1 Requestor Address Bits 0 7 REGISTER EXP ADDRESS AT ADDRESS ACCESS D7 D6 D5 D4 D3 D2 D1 D0 R W BP 1 Cha...

Page 56: ...S AT ADDRESS ACCESS D7 D6 D5 D4 D3 D2 D1 D0 DMA1REQ3 0F013h R W BP 1 Channel 0 requestor address bit 24 Channel 0 requestor address bit 25 Reserved ND ND Reserved Channel 1 requestor address bits 24 2...

Page 57: ...ADDRESS AT ADDRESS ACCESS D7 D6 D5 D4 D3 D2 D1 D0 DMA0TAR2 0F087h R W Channel 0 target address bit 16 Channel 0 target address bit 17 Channel 0 target address bit 18 Channel 0 target address bit 19 Ch...

Page 58: ...el 1 target address bit 7 ND ND ND ND ND ND ND ND Channel 1 target address bits 0 7 0002h Channel 1 Target Address Bits 0 7 REGISTER ADDRESS AT ADDRESS ACCESS D7 D6 D5 D4 D3 D2 D1 D0 DMA1TAR1 0F002h R...

Page 59: ...ISTER ADDRESS AT ADDRESS ACCESS D7 D6 D5 D4 D3 D2 D1 D0 DMA1TAR3 0F085h R W Channel 1 target address bit 24 Channel 1 target address bit 25 Reserved ND ND Reserved Channel 1 target address bits 24 25...

Page 60: ...l 0 byte count bit 15 ND ND ND ND ND ND ND ND Channel 0 byte count bits 8 15 0001h Channel 0 Byte Count Bits 8 15 REGISTER ADDRESS AT ADDRESS ACCESS D7 D6 D5 D4 D3 D2 D1 D0 DMA0BYC2 0F098h R W Channel...

Page 61: ...it 6 Channel 1 byte count bit 7 ND ND ND ND ND ND ND ND Channel 1 byte count bits 0 7 0003h Channel 1 Byte Count Bits 0 7 REGISTER ADDRESS AT ADDRESS ACCESS D7 D6 D5 D4 D3 D2 D1 D0 DMA1BYC1 0F003h R W...

Page 62: ...ndividually The DMA controller sets bits in this register to indicate that a channel has a hardware request pending or that a channel s byte count has expired REGISTER ADDRESS AT ADDRESS ACCESS D7 D6...

Page 63: ...priority Reserved write 0 s to these bits 0008h DMA command register 1 DMA Command Register 1 The DMACMD2 register is used to select the type of DRQn and EOP sampling used and to assign a particular...

Page 64: ...Bits D7 D2 affect channel 1 0 Bits D7 D2 affect channel 0 Reserved Transfer direction 00 target is read nothing is written test mode 1 Auto initialize channel 0 Do not auto initialize channel 1 targe...

Page 65: ...re DMA service requests Software requests are subject to bus control priority arbitration with all other software and hardware requests A software request activates the internal channel request signal...

Page 66: ...SK 0F00Ah DMA single channel mask register Reserved 1 0 0 Reserved DMA Single Channel Mask Register DMA Group Channel Mask Use the DMAGRPMSK register to enable or disable hardware requests for both ch...

Page 67: ...nsfers 1 Set up the chaining interrupt DMAINT service routine 2 Configure the channel for single buffer transfer mode 3 Program the mode registers 4 Program the target address requestor address and by...

Page 68: ...to channel 0 This bit is cleared when new transfer information is written to the channel Writing to the most significant bit of the target address clears this bit Outside chaining Reserved DMAIS 0F019...

Page 69: ...TER ADDRESS AT ADDRESS ACCESS D7 D6 D5 D4 D3 D2 D1 D0 R W 1 All bits of channel 0 target address and byte count inc dec 0 Only lower 16 bits of channel 0 target address and byte count inc dec DMAOVFE...

Page 70: ...ap year compensation Daylight Savings Time compensation Periodic Alarm and Update Ended interrupts Battery backed PROGRAMMABLE REGISTERS The real time clock includes 64 register locations These regist...

Page 71: ...nge 0h Time Seconds 0 59 1h Alarm Seconds 0 59 2h Time Minutes 0 59 3h Alarm Minutes 0 59 4h Time Hours 12 hour mode 1 12 4h Time Hours 24 hour mode 0 23 5h Alarm Hours 0 23 6h Day of Week 1 7 7h Date...

Page 72: ...Access Read and Write 0000 No Interrupts 0 1 UIP 0001 3 90625 ms 0010 7 8125 ms 0011 122 070 us 0100 244 141 us 0101 488 281 us 0110 976 562 us 0111 1 953125 ms 1000 3 90625 ms 1001 7 8125 ms 1010 15...

Page 73: ...ary Update End Interrupt 0 Disabled 1 Enabled Alarm Interrupt Enable 0 Disabled 1 Enabled Periodic Interrupt Enable 0 Disabled 1 Enabled Cycle Update 0 Real Time 1 Latch Time Register B Register C Reg...

Page 74: ...Valid RAM 0 Invalid 1 Valid Register D ADDITIONAL INFORMATION Refer to the National Semiconductor PC87306 datasheet for more information on the real time clock operating modes The product folder for...

Page 75: ...eed for a 12 V supply The serial ports include a complete set of handshaking and modem control signals maskable interrupt generation and data transfer rates up to 115 Kbaud Two of the serial ports are...

Page 76: ...R4 IR4 COM2 IR3 IR3 COM3 IR4 IR13 COM4 IR3 IR9 Handshake Signals The PC architecture includes Transmit Data TXD Receive Data RXD Request To Send RTS Clear To Send CTS Data Set Ready DSR Data Terminal...

Page 77: ...W13 W12 COM1 RS 485 Architecture Signal Condition RxD Signal Condition J1 78 W30 W31 System Register 2 Bit 3 TxD DTR J1 77 J1 80 J1 79 W15 W14 COM2 RS 485 Architecture Serial Channel Interface The ser...

Page 78: ...ffer Read 03F8h DIV 0 Transmit Buffer Write 03F8h DIV 1 Divisor Latch LSB Read Write 03F9h DIV 0 Interrupt Control Read Write 03F9h DIV 1 Divisor Latch MSB Read Write 03FAh Interrupt Status Read 03FBh...

Page 79: ...192 120h 0 1200 96 60h 0 1800 64 40h 0 2000 58 3Ah 0 69 2400 48 30h 0 3600 32 20h 0 4800 24 18h 0 7200 16 10h 0 9600 12 Ch 0 19200 6 6h 0 38400 3 3h 0 56000 2 2h 2 86 57600 2 2h 0 115200 1 1h 0 Divis...

Page 80: ...ch MSB Interrupt Control Register Register Interrupt Control Address 3F9h DIV 0 Access Read and Write 0 MSI LSI TBI RBI 7 6 5 4 3 2 1 0 0 0 0 Receive Buffer Interrupt 0 Disabled 1 Enabled Transmit Buf...

Page 81: ...Address 3FAh Interrupt Access Read 0 Active 0 0 0 INT 1 Inactive Interrupt Source 000 Modem Status Clear to send Data set ready Ring indicator Data carrier detect 001 Transmit Buffer 010 Receive Buff...

Page 82: ...bits DIV BRK PTS PTE STP 01 6 bits 10 7 bits 11 8 bits Stop Bits 0 1 bit 1 2 0 bits for Length 6 7 or 8 1 5 bits for Length 5 Parity Selection 0 Odd 1 Even Break Sequence 0 Do not transmit 1 Transmit...

Page 83: ...uence 0 Not detected 1 Detected Transmit Holding Register 0 Full 1 Empty Transmit Buffer 0 Full 1 Empty Line Status Register Modem Control Register 7 6 5 4 3 2 1 0 Register Modem Control Address 2FC 3...

Page 84: ...0 Negative voltage 1 Positive voltage Data Carrier Detect 0 Negative voltage 1 Positive voltage Delta Data Set Ready 0 No transition 1 Transition Modem Status Register ADDITIONAL INFORMATION Refer to...

Page 85: ...rinter interface Line Printer Data Register Register Line Printer Data Address 378h Access Read and Write D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 Line Printer Data Register Line Printer Status Registe...

Page 86: ...1 Yes 1 Select Input 0 Off line 1 On line Initialize Printer 0 Reset 1 No reset Direction Write only 0 To printer 1 From printer Interrupts 0 Disabled 1 Enabled Line Printer Control Register ADDITIONA...

Page 87: ...2 mA sink current Software programmable input debounce Stable outputs during power up and reset Continuous data transfer rates up to 1 Mbyte second Software programmable event sense interrupt generati...

Page 88: ...nector J4 The output buffer is an inverting open collector device with 12 mA of sink current and glitch free operation during power cycles The inversion means that a logical 0 written to the parallel...

Page 89: ...ated with it The three I O ports at 78h 79h and 7Ah are available through connector J4 Refer to Appendix B Specifications for the connector pin assignments The three I O ports at 7Bh 7Ch and 7Dh are d...

Page 90: ...T 8904 for enhanced operation at BIOS revision 4 41 or later Enhanced Bank 0 I O Port Addressing Address Register Read Operation Write Operation 0078h Port 0 Data MOD00 MOD07 MOD00 MOD07 0079h Port 1...

Page 91: ...ank Address Status Control 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Port 0 1 and 2 Data Mode Standard and Enhanced Bank 0 Address 78h 7Ah Access Read and Write Port Dat...

Page 92: ...is an invalid state and should never be written to the Mask Register 7 6 5 4 3 2 1 0 Register Port 0 1 and 2 Event Sense Read Mode Enhanced Bank 1 Address 78 7Ah Access Read and Write Event Sense Stat...

Page 93: ...2 1 Port 0 Port Event Sense Manage Register Note The polarity of the event sense logic must be set prior to enabling the event input logic in enhanced mode 7 6 5 4 3 2 1 0 Bank Bank Bank Address 00 B...

Page 94: ...7 6 5 4 3 2 1 0 0 0 Port Port Port 2 1 0 Port 2 Port 1 Port 0 Duration 00 4 s 01 64 s 10 1 ms 11 8 ms Register Debounce Duration Mode Enhanced Bank 2 Address 79h Access Read and Write Debounce Duratio...

Page 95: ...3 2 1 0 0 0 0 2 1 0 Port Write Inhibit 0 Inactive 1 Active Port Port Port Mode Enhanced Bank 0 Address 7Fh Access Read and Write Register Mask Bank Bank Address 00 Bank 0 01 Bank 1 10 Bank 2 11 Undefi...

Page 96: ...s dedicated to input operation must remain programmed with a logical 0 to prevent contention with the input device Bits dedicated to output operation have readback capabilities PROGRAMMABLE REGISTERS...

Page 97: ...manent Master Operation 0 Temporary 1 Permanent Power Fail NMI 0 Active 1 Inactive STD Bus NMI 0 Active 1 Inactive Watchdog Timer NMI 0 Active 1 Inactive Local Bus Expansion 00 Type 0 01 Type 1 10 Typ...

Page 98: ...board Interrupt 0 Local 1 System Com 1 Interface 0 RS 485 1 RS 232 Com 2 Interface 0 RS 485 1 RS 232 Video Mux 0 Enable 1 Disable VPP Generator 0 Enable 1 Disable Bus Request Destination 0 Enable 1 Di...

Page 99: ...med with a logical one to enable the second stage to begin counting After the second stage counts down to zero a reset is generated If the ZT 8904 is configured as a permanent master the reset extends...

Page 100: ...OR 1 RST I R Q RST 16 11 100 Ms Minimum 400 Ms Typical 600 Ms Maximum Watchdog Timer Architecture PROGRAMMABLE REGISTERS The four register groups associated with the first stage of the watchdog timer...

Page 101: ...e 1 F01Eh 2 0FE1h 15 14 13 12 11 10 9 8 Register Watchdog Clear Address F4C8h Access Write Only Watchdog Timer Clear Register Watchdog Timer Status Register The Watchdog Timer Status register contains...

Page 102: ...the Watchdog Reload registers to the Watchdog Timer registers Register Access Address 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 WDT Count High F4C4h Read WC31 WC30 WC29 WC28 WC27 WC26 WC25 WC24 WC31 WC23...

Page 103: ...gh F4C0h Read and Write Read after lockout Current WDT Reload High WR15 WR14 WR13 WR12 WR11 WR10 WR9 WR8 WR7 WR6 WR5 WR4 WR3 WR2 WR1 WR0 Register Access Address 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 W...

Page 104: ...r STD bus video solutions by running with four times the data width and more than four times the operating frequency Major features of the video adapters are listed below Refer to the zVID manual for...

Page 105: ...ation performance by as much as 10 on Whetstone and Livermore benchmarks The numeric data processors qualified to work in the ZT 8904 are listed below Note that neither of these devices meet the exten...

Page 106: ...ster as the multiple master interrupt The following code demonstrates how to turn the red LED on and off without corrupting the multiple master interrupt The multiple master interrupt is a bidirection...

Page 107: ...15 Programmable LED 107 led_off turns off the led led_off pushf cli input_7d and al not 80h out 07dh al popf ret...

Page 108: ...gure The pin assignments for connector J3 are given in Appendix B Specifications AC Wall Transformer Installation In operation a non maskable interrupt is generated when AC power falls below 95 VRMS T...

Page 109: ...here a is one selection and b is another Jumper locations are illustrated in the Customer Jumper Configuration figure following use this figure to document your jumper configuration if it differs from...

Page 110: ...W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 a b ZT 8904 ZIATECH DOS Factory Default Configuration W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23...

Page 111: ...sor IN Installed OUT Removed W9 11 Non Maskable Interrupts arm the AC power fail STD bus and watchdog timer interrupts for non maskable interrupt generation Jumper installation connects the non maskab...

Page 112: ...c application These jumpers do not apply to the ZT 8903 W12 W13 COM1 Duplex IN IN Half duplex two wire OUT OUT Full Duplex four wire W14 W15 COM2 Duplex IN IN Half Duplex two wire OUT OUT Full Duplex...

Page 113: ...not used in the application must be masked in software Jumper Installed Interrupt Source Interrupt W17a STD bus INTRQ4 IR5 W17b J2 pin 6 IR5 W18a STD bus INTRQ2 IR6 W18b J2 pin 8 IR6 W19a Printer IR7...

Page 114: ...ct and Clear To Send are not available for COM2 If DMA channel 1 is used to support local DMA such as the 1284 printer port Transmit Data and Receive Data are not available for COM2 When W24 and W25 a...

Page 115: ...ured for RS 485 the following jumpers adjust the RS 485 architecture to a specific application These jumpers do not apply to the ZT 8903 W28a W28b COM1 Transmit Enable IN OUT COM1 DTR OUT IN COM1 TXD...

Page 116: ...ing characteristics battery backup characteristics and STD bus loading characteristics Absolute Maximum Ratings Supply Voltage Vcc 0 to 7 V Supply Voltage AUX V Not used Supply Voltage AUX V Not used...

Page 117: ...topologies STD Bus Loading Characteristics The unit load is a convenient method for specifying the input and output drive capability of STD bus cards With this method one unit load is equal to one LST...

Page 118: ...NT SIDE OUTPUT DRIVE INPUT LOAD MNEMONIC P2 P4 P6 P8 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 P30 P32 P34 P36 P38 P40 P42 P44 P46 P48 P50 P52 P56 P54 P53 P55 P47 P49 P51 P39 P41 P43 P45 P31 P33 P35 P37...

Page 119: ...BE0 MEM16 M IO D17 D16 GND IRQx D20 GND D19 D18 D24 D23 D22 D21 GND D27 D26 D25 XA16 NOWS 5 VDC DAKx GND XA19 XA18 XA17 PIN COMPONENT SIDE OUTPUT DRIVE MNEMONIC INPUT LOAD E2 E4 E8 E6 E10 E12 E14 E16...

Page 120: ...e shown in the Board Dimensions figure following and are outlined below Board Length 16 51 0 063 cm 6 500 0 025 inches Board Width 11 43 0 038 cm 4 500 0 015 inches Board Thickness 0 158 0 013 cm 0 06...

Page 121: ...the ZT 8904 and the STD 80 bus This connector is a 56 pin dual 28 pin card edge connector with fingers on 0 125 inch contact spacing The mating connector is a Viking 3VH28 1CNK5 or equivalent for the...

Page 122: ...3 E14 P01 P02 E15 E16 P03 P04 E17 E18 P05 P06 E19 E20 P07 P08 E21 E22 P09 P10 E23 E24 P11 P12 E25 E26 P13 P14 E27 E28 P15 P16 E29 E30 P17 P18 E31 E32 P19 P20 E33 E34 P21 P22 E35 E36 P23 P24 E37 E38 P2...

Page 123: ...tion for the serial and 1284 parallel ports The mating connector is an AMP 104892 8 or equivalent J1 Peripheral Pinout Pin Signal Type Description Pin Signal Type Description 1 COM4 DCD In Data Carrie...

Page 124: ...st To Send 64 GND Ground 25 COM2 TXD Out Transmit Data 65 ACK In Acknowledge 26 COM2 CTS In Clear To Send 66 GND Ground 27 COM2 DTR Out Data Terminal Ready 67 BUSY In Busy 28 COM2 RIN In Ring Indicato...

Page 125: ...ane Interrupt Pinout Pin Signal Type Description 1 GND Ground 2 NC In Not connected 3 GND Ground 4 NC In Not connected 5 GND Ground 6 FP5 In Interrupt level 5 7 GND Ground 8 FP6 In Interrupt level 6 9...

Page 126: ...ail detection feature are available through this connector The pin assignments are given in the J3 AC Power Fail Pinout table following The mating connector is a Molex 39 01 0023 or equivalent The mat...

Page 127: ...5 MOD21 In Out Port 7A bit 5 30 GND Ground 6 GND Ground 31 MOD08 In Out Port 79 bit 0 7 MOD20 In Out Port 7A bit 4 32 GND Ground 8 GND Ground 33 MOD07 In Out Port 78 bit 7 9 MOD19 In Out Port 7A bit...

Page 128: ...CPU Address 33 CE7 Out Chip select 7 7 A7 Out CPU Address 34 WE Out Write strobe 8 A8 Out CPU Address 35 OE Out Output enable 9 A9 Out CPU Address 36 RSV Reserved 10 A10 Out CPU Address 37 D15 In Out...

Page 129: ...PU Data 4 GND Ground 54 D15 In Out CPU Data 5 A04 Out CPU Address 55 D16 In Out CPU Data 6 A03 Out CPU Address 56 D17 In Out CPU Data 7 A06 Out CPU Address 57 D18 In Out CPU Data 8 A05 Out CPU Address...

Page 130: ...34 A29 Out CPU Address 84 BLAST Out Burst Last 35 A30 Out CPU Address 85 M I Out Memory I O 36 A31 Out CPU Address 86 LBA In Local Bus Ack 37 D00 In Out CPU Data 87 W R Out Write Read 38 GND Ground 8...

Page 131: ...is not used The pin assignments are given in the following table J7 Auxiliary Power Pinout The multiple source board mount connectors and associated mating connectors are shown below Board Connector...

Page 132: ...ed 6 D9 In Out Latched Data 28 ALE Out Address Latch 7 D5 In Out Latched Data 29 RSVD Reserved 8 D10 In Out Latched Data 30 GND Ground 9 D4 In Out Latched Data 31 IRQ In Interrupt 10 D11 In Out Latche...

Page 133: ...Desktop Video and Keyboard Cable ZT 90168 Multiple zVID2 ZT 90200 Quad Serial and Printer Cable for ZT 8904 and ZT 89CT04 ZT 90203 Dual Serial and Printer Cable for the ZT 8903 TB ANSLEY 171 50 50 CO...

Page 134: ...Covers P1 TB ANSLEY 622 1030 10 Pin Female w Polarization 4 Places COM 4 COM 3 COM 2 COM 1 TB ANSLEY 622 09PMI 9 Pin Male 4 Places J2 LPT J1 Truncate Conductors 10 20 30 40 After 10 Pin Female Do Not...

Page 135: ...R EQUIV 3 RED WIRE PIN 1 HEAT SHRINK TUBING 1 4 DIAMETER BLACK ALPHA FIT 221 1 4 1 2 PIN ASSIGNMENT CHART P2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 10 12 14 7 9 11 13 7 6 8 P2 VIDEO CONN J1 PIN 49 PIN 50...

Page 136: ...E WIRE FRONT VIEW SAMTEC TCSD 25 01 N 3M 3625 14 GRAY 14 CONDUCTOR 1mm CENTERS 28 GAUGE STRANDED FLAT CABLE OR EQUIV 1 2 3 CRIMP STRAIN RELIEF SIDE VIEW 3 4 HEAT SHRINK TUBING 3 16 DIAMETER BLACK ALPH...

Page 137: ...DIN CONNECTOR 1 4 5 14 P2 P1 10 J1 SAMTEC TCSD 25 01 N J2 J3 J4 J5 J6 J7 6 6 6 6 6 6 3M 3625 14 GRAY 14 CONDUCTOR 28 GAUGE 1mm CENTERS STRANDED FLAT CABLE OR EQUIV 3 1 2 HEAT SHRINK TUBING 1 4 DIAMET...

Page 138: ...for 5V no connection to 9 Pin Male COM1 2 Justify 6 Conductors toward Pin 1 3 KEEP CABLE AS SINGLE PIECE FOR FIRST 3 BEFORE SEPARATING TB ANSLEY 171 40 Gray 40 Wire 28 Gauge Stranded Flat Cable or Eq...

Page 139: ...ts When this happens Vcc is effectively shorted to ground The only way to remove the latchup condition is to shut off the power supply If a large current is allowed to flow through the chip its operat...

Page 140: ...8904 Interface Cable 24 Position or Custom Application Vcc 1Amp 24 Figure 1 I O Rack Vcc and Ground Supplied through Interface Cable Correct Power Supply Sequence Signal Level Matched However if a po...

Page 141: ...lay controlling the external power supply directly from Vcc and ground supplied by the interface cable Another solution is to utilize the same switch to control the computer s power supply and the ext...

Page 142: ...e most convenient way of connecting a common ground is to use the interface cable Figures 5 6 and 7 below illustrate correct ground connections The second cause of mismatch occurs when the two power s...

Page 143: ...components to malfunction A pullup termination resistor is used to increase the rise time Input rise times must be kept to less than 50 ns Given a maximum chip capacitance of 10 pF a 5k resistor is th...

Page 144: ...ly that are easily compatible with the PIA given a 1k pullup Ziatech 2 2K 24V 10mA 1K HCPL 2630 16C50A PIA Figure 8 PIA to Optocoupler Interface Example Inductive Coupling Inductive coupling on I O li...

Page 145: ...ferrite bead forms an additional low pass filter and is entirely optional The 1k pullup ensures adequate rise time on the signal The fuse acts as additional insurance against catastrophic events that...

Page 146: ...541 0488 FAX 805 541 5088 RELIABILITY Ziatech takes extra care in the design of the product in order to ensure reliability The product was designed in top down fashion using the latest in hardware an...

Page 147: ...pired 3 Pack the board in anti static material and ship in a sturdy cardboard box with enough packing material to adequately cushion it Note Any product returned to Ziatech improperly packed will imme...

Page 148: ...ed QNX is a registered trademark of Quantum Software Systems Ltd STD 32 is a registered trademark of Ziatech Corporation STD 32 STAR SYSTEM is a trademark of Ziatech Corporation TransZorb is a registe...

Page 149: ...1050 Southwood Drive San Luis Obispo CA 93401 USA Tel 805 541 0488 FAX 805 541 5088 E Mail tech_support ziatech com Internet http www ziatech com...

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