4. Interrupt Controller
37
SLCT
SMM
7
6
5
4
3
2
1
0
Register: OCW3
Address: Base + 0
Read Register
Access: Write
00 Do not use
0
1
01 Do not use
10 Select IR register
11 Select IS register
Mask Selection
00 Do not use
01 Do not use
10 Standard mask
0
P
Poll Command
0 No poll
1 Poll
11 Special mask
Operational Register OCW3
Status Registers (IRR, ISR, IPR)
Each interrupt controller includes three status registers. A status register is selected by
programming the first three bits of OCW3.
Request
7
6
5
4
3
2
1
0
Register: IRR
Address: Base + 0
Input Request Pending
Access: Read
0 No
1 Yes
Status Register IRR
Service
7
6
5
4
3
2
1
0
Register: ISR
Address: Base + 0
Input In Service
Access: Read
0 No
1 Yes
Status Register ISR
