Theory of Operation
16K byte Page
16K byte Page
16K byte Page Frame
16K byte Page Frame
2 Mbytes
0 Kbytes
Map Register
1
1
1 Mbyte
0 Kbytes
PC Logical Address Space
Physical Paged Memory
Figure 3–2. Logical to Physical Address Mapping.
Map Registers
Each page frame in the logical address space has an associated Map
Register on the ZT 8825. 64 Map Registers are used in 20-bit address
systems. 1,024 Map Registers are available in 24-bit address systems.
In addition, a complete alternate set of Map Registers can be loaded at
the same time as the primary set and switched in under software
control (see "Setting the Map Register" on page 3-18). The physical
registers are composed of two 4K x 4 SRAMs with 35 ns access
times. Memory address bits A14-A19 (A14-A23 for 24-bit systems)
form the index number of the Map Register for each 16K block.
3-15
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