Theory of Operation
The I/O base address for the board may be placed at one of 256
locations in the 64 Kbyte I/O address space of the STD-80 Series bus.
The base address can be defined by either 8 or 16 bits (removing
Jumper W6 restricts it to 8 bits).
Address lines A15-A0 supply the 16 bits of I/O address to the
ZT 8825 (see Table 3-3). A15-A12 are jumper configurable. A11-A8
are hardwired to 1110b. A7-A4 are jumper configurable. A3 is
hardwired to a logical 1. A2 is not decoded. A1-A0 define the four
unique addresses (000b, 001b, 010b, and 011b) used on the ZT 8825
(see Table 3-4).
Note: Since A2 is not decoded, four addresses (100b, 101b, 110b, and
111b) are redundantly mapped and should not be used.
Table 3-4
ZT 8825 I/O Registers.
Base+ Default
Description
000
EE68h
Low order six bits of Map Register
address (write only)
001
EE69h
High order four bits of Map Register
address (write only)
010
EE6Ah
Data to/from Map Register previously
addressed (read/write)
011
EE6Bh
Configuration Register (write only, reset
to 0 at power-on)
3-11
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