Theory of Operation
WAIT STATES
You may select either zero wait states or one wait state for the board.
If one wait state is selected, the ZT 8825 requests a wait state only for
16 Kbyte blocks of memory that you have programmed as enabled.
All chips on the board must use the same number of wait states; the
slowest chip, therefore, determines the speed of the board.
Generally speaking, devices with a maximum access time of 120 ns
will work on the ZT 8825 with no wait states when used with an
8 MHz STD-80 Series CPU board, such as the Ziatech ZT 8809. For
5 MHz STD-80 Series CPUs (for example, with a ZT 8808), access
times of 290 ns or less will need no wait states.
For no wait states, the ZT 88CT25 requires devices of < 250 ns for
5 MHz STD-80 Series CPUs and
≤
80 ns for 8 MHz STD-80 Series
CPUs. Note that when a ZT 88CT25 is used with a ZT 8817 or any
other CPU that requires WAITRQ* to be asserted by mid T2, the
CPU must insert the wait state. The ZT 88CT25 wait state generator
will not be fast enough at 8 MHz to meet the ZT 8817 requirement.
Access time requirements are listed in the table on page 5-8. Consult
your CPU board manual to answer any questions.
WRITE PROTECTION
The ZT 8825 has a write-protect switch (SW2) to assist in program
debugging. When this toggle switch is positioned down (default)
toward the board, the write signal is inhibited, preventing loss of data
should a program run wild. This switch is located at the top of the
board for easy access.
Write protection can also be controlled through software by
manipulating bit 3 of the Configuration Register. Setting bit 3 to a
logical 0 will inhibit writing to the memory (refer to Figure 3-4 on
page 3-17). This bit is reset to zero at power-on time and by a system
reset. SW2 must be enabled and Configuration Register bit 3 must be
a logical 1 to write to the memory.
3-6
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
