Fujitsu MHA2021AT Product Manual Download Page 1

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C141-E042-01EN

MHA2021AT, MHA2032AT

DISK DRIVES

PRODUCT MANUAL

Summary of Contents for MHA2021AT

Page 1: ...C141 E042 01EN MHA2021AT MHA2032AT DISK DRIVES PRODUCT MANUAL ...

Page 2: ...mes no liability to any party for any damage caused by any error or omission contained in this manual its updates or supplements whether such errors or omissions result from negligence accident or any other cause In addition FUJITSU assumes no liability with respect to the application or use of any product or system in accordance with the descriptions or instructions contained herein including any...

Page 3: ...C141 E042 01EN Revision History 1 1 Edition Date Revised section 1 Added Deleted Altered Details 01 1997 07 15 1 Section s with asterisk refer to the previous edition when those were deleted ...

Page 4: ...T and MHA2032AT and describes their features CHAPTER 2 Drive Configuration This chapter describes the internal configurations of the MHA2021AT and MHA2032AT and the configuration of the systems in which they operate CHAPTER 3 Drive Installation This chapter describes the external dimensions installation conditions and switch settings of the MHA2021AT and MHA2032AT CHAPTER 4 Theory of Drive Operati...

Page 5: ...er does not perform the procedure correctly This indicates information that could help the user use the product more efficiently In the text the alert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption Avoid mounting the disk drive nea...

Page 6: ...ward it to the address described in the sheet Liability Exception Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes outside the disk driv...

Page 7: ...personal injury if the user does not perform the procedure correctly Also damage to the predate or other property may occur if the user does not perform the procedure correctly Task Alert message Page Normal Operation Data corruption Avoid mounting the disk near strong magnetic soures such as loud speakers Ensure that the disk drive is not affected by extrnal magnetic fields 3 6 ...

Page 8: ...ons summary 1 4 1 2 2 Model and product number 1 5 1 3 Power Requirements 1 5 1 4 Environmental Specifications 1 7 1 5 Acoustic Noise 1 7 1 6 Shock and Vibration 1 8 1 7 Reliability 1 8 1 8 Error Rate 1 9 1 9 Media Defects 1 9 CHAPTER 2 Device Configuration 2 1 2 1 Device Configuration 2 2 2 2 System Configuration 2 4 2 2 1 ATA interface 2 4 2 2 2 1 drive connection 2 4 2 2 3 2 drives connection 2...

Page 9: ...ng 3 10 3 4 3 Master drive slave drive setting 3 10 3 4 4 CSEL setting 3 11 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Head 4 2 4 2 3 Spindle 4 3 4 2 4 Actuator 4 3 4 2 5 Air filter 4 3 4 3 Circuit Configuration 4 4 4 4 Power on Sequence 4 6 4 5 Self calibration 4 7 4 5 1 Self calibration contents 4 7 4 5 2 Execution timing of self calibrati...

Page 10: ...face 5 6 5 2 1 I O registers 5 6 5 2 2 Command block registers 5 8 5 2 3 Control block registers 5 13 5 3 Host Commands 5 13 5 3 1 Command code and parameters 5 14 5 3 2 Command descriptions 5 16 5 3 3 Error posting 5 67 5 4 Command Protocol 5 69 5 4 1 Data transferring commands from device to host 5 69 5 4 2 Data transferring commands from host to device 5 71 5 4 3 Commands without data transfer ...

Page 11: ...ddress Translation 6 7 6 2 1 Default parameters 6 7 6 2 2 Logical address 6 8 6 3 Power Save 6 9 6 3 1 Power save mode 6 9 6 3 2 Power commands 6 11 6 4 Defect Management 6 11 6 4 1 Spare area 6 12 6 4 2 Alternating defective sectors 6 12 6 5 Read Ahead Cache 6 14 6 5 1 Data buffer configuration 6 14 6 5 2 Caching operation 6 14 6 5 3 Usage of read segment 6 16 6 6 Write Cache 6 22 Glossary GL 1 A...

Page 12: ...10 Factory default setting 3 10 Figure 3 11 Jumper setting of master or slave device 3 10 Figure 3 12 CSEL setting 3 11 Figure 3 13 Example 1 of Cable Select 3 11 Figure 3 14 Example 2 of Cable Select 3 12 Figure 4 1 Head structure 4 3 Figure 4 2 Circuit Configuration 4 5 Figure 4 3 Power on operation sequence 4 7 Figure 4 4 Read write circuit block diagram 4 11 Figure 4 5 Frequency characteristic...

Page 13: ...le 1 2 Model names and product numbers 1 5 Table 1 3 Current and power dissipation 1 6 Table 1 4 Environmental specifications 1 7 Table 1 5 Acoustic noise specification 1 7 Table 1 6 Shock and vibration specification 1 8 Table 3 1 Surface temperature measurement points and standard values 3 5 Table 3 2 Cable connector specifications 3 8 Table 4 1 Self calibration execution timechart 4 9 Table 4 2 ...

Page 14: ...password 5 59 Table 5 11 Contents of SECURITY SET PASSWORD data 5 64 Table 5 12 Relationship between combination of Identifier and Security level and operation of the lock function 5 65 Table 5 13 Command code and parameters 5 67 Table 6 1 Default parameters 6 7 ...

Page 15: ...1 6 Shock and Vibration 1 7 Reliability 1 8 Error Rate 1 9 Media Defects Overview and features are described in this chapter and specifications and power requirement are described The MHA2021AT and MHA2032AT are 2 5 inch hard disk drives with built in disk controllers These disk drives use the AT bus hard disk interface protocol and are compact and reliable ...

Page 16: ...4 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 13 ms at read 1 1 2 Adaptability 1 Power save mode The power save mode feature for idle operation stand by and sleep modes makes the disk drive ideal for applications where power consumption is a factor 2 Wide temperature range The di...

Page 17: ...s to the data requested by the next read command the data in the buffer can be transferred instead 4 Master slave The disk drive can be connected to ATA interface as daisy chain configuration Drive 0 is a master device drive 1 is a slave device 5 Error correction and retry by ECC If a recoverable error occurs the disk drive itself attempts error recovery The ECC has improved buffer error correctio...

Page 18: ...nal Speed 4 000 rpm 1 Average Latency 7 5 ms Positioning time read and seek Minimum Track to Track Average Maximum Full 2 5 ms typ Read 13 ms typ 23 ms typ Start Stop time Start 0 rpm to Drive Read Stop at Power Down Typ 5 sec Max 10 sec Typ 5 sec Max 15 sec when the command is stopped when the power is off Interface ATA 3 Max Cable length 0 46 m Data Transfer Rate To From Media To From Host 4 93 ...

Page 19: ...eads No of Sectors MHA2021AT 2 167 60 MB 4 200 16 63 MHA2032AT 3 251 40 MB 6 300 16 63 1 2 2 Model and product number Table 1 2 lists the model names and product numbers Table 1 2 Model names and product numbers Model Name Capacity user area Mounting screw Order No MHA2021AT 2 16 GB M3 depth 3 CA01640 B040 MHA2032AT 3 25 GB M3 depth 3 CA01640 B060 1 3 Power Requirements 1 Input Voltage 5 V 5 2 Rip...

Page 20: ... 0 38 W Sleep 0 03 AT B D T B D 0 15 W 1 Current at starting spindle motor 2 Power requirements reflect nominal values for 5V power 3 At 30 disk accessing 4 Current fluctuation Typ at 5V when power is turned on Figure 1 1 Current fluctuation Typ at 5V when power is turned on 5 Power on off sequence The voltage detector circuit monitors 5 V The circuit does not allow a write signal if either voltag...

Page 21: ...C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non condensing 5 to 95 RH Non condensing 29 C Altitude relative to sea level Operating Non operating 300 to 3 000 m 200 to 10000 ft 300 to 12 000 m 200 to 40000 ft 1 5 Acoustic Noise Table 1 5 lists the acoustic noise specification Table 1 5 Acoustic noise specification Sound Pressure ...

Page 22: ...tween failures MTBF The mean time between failures MTBF is 300 000 H or more operation 24 hours day 7 days week This does not include failures occurring during the first three months after installation MTBF is defined as follows Total operation time in all fields MTBF H number of device failure in all fields Disk drive defects refers to defects that involve repair readjustment or replacement Disk ...

Page 23: ...nown defects for which alternative blocks can be assigned are not included in the error rate count below It is assumed that the data blocks to be accessed are evenly distributed on the disk media 1 Unrecoverable read error Read errors that cannot be recovered by maximum 126 times read retries without user s retry and ECC corrections shall occur no more than 10 times when reading data of 1014 bits ...

Page 24: ... 1 CHAPTER 2 Device Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate ...

Page 25: ... diameter is 20 mm The number of disks used varies with the model as described below The disks are rated at over 50 000 start stop operations MHA2021AT 2 disk MHA2032AT 3 disks 2 Head The heads are of the contact start stop CSS type The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts Figure 2 2 illustrates the configuration of the disks and...

Page 26: ...tuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays in the specific CSS zone on the disk and is fixed ...

Page 27: ...s a LSI chip for the read write preamplifier It improves data reliability by preventing errors caused by external noise 7 Controller circuit The controller circuit consists of an LSI chip to improve reliability The high speed microprocessor unit MPU achieves a high performance AT controller 2 2 System Configuration 2 2 1 ATA interface Figures 2 3 and 2 4 show the ATA interface system configuration...

Page 28: ...river and receiver ATA is an abbreviation of AT attachment The disk drive is conformed to the ATA 3 interface At high speed data transfer PIO mode 3 mode 4 or DMA mode 2 occurence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including t...

Page 29: ...n Conditions 3 1 Dimensions 3 2 Mounting 3 3 Cable Connections 3 4 Jumper Settings This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives ...

Page 30: ...Installation Conditions 3 2 C141 E042 01EN 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm Figure 3 1 Dimensions ...

Page 31: ...41 E042 01EN 3 3 3 2 Mounting 1 Orientation Figure 3 2 illustrates the allowable orientations for the disk drive Figure 3 2 Orientation e Vertical 3 f Vertical 4 c Vertical 1 d Vertical 2 b Horizontal 1 a Horizontal 1 ...

Page 32: ...not exceed 3 kgcm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of side mounting Do not use the center hole For screw length see Figure 3 3 Figure 3 3 Mounting frame structure Screw Screw Details of B Details of A 3 0 or less 3 0 or less Frame of system cabinet Frame of system cabine...

Page 33: ...emperature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 4 shows the temperature measurement point Figure 3 4 Surface temperature m...

Page 34: ...e areas during and after installation Figure 3 5 Service area 6 External magnetic fields Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Mounting screw hole Mounting screw hole Cable connection ...

Page 35: ... Connections 3 3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 6 shows the locations of these connectors and terminals Figure 3 6 Connector locations Connector setting pins PCA ...

Page 36: ...able 44 pin type FV08 A440 Junkosha For the host interface cable use a ribbon cable A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines This is because the interface is designed for ribbon cables and not for cables carrying differential signals 3 3 3 Device connection Figure 3 7 shows how to connect the devices Figure 3 7 Cable ...

Page 37: ...re 3 8 shows the pin assignment of the power supply connector CN1 Figure 3 8 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 9 shows the location of the jumpers to select drive configuration and functions Figure 3 9 Jumper location ...

Page 38: ...ure 3 10 shows the default setting position at the factory Figure 3 10 Factory default setting 3 4 3 Master drive slave drive setting Master device device 0 or slave device device 1 is selected Figure 3 11 Jumper setting of master or slave device Note Pins A and C should be open ...

Page 39: ... unique interface cables By connecting the CSEL of the master device to the CSEL Line conducer of the cable and connecting it to ground further the CSEL is set to low level The device is identified as a master device At this time the CSEL of the slave device does not have a conductor Thus since the slave device is not connected to the CSEL conductor the CSEL is set to high level The device is iden...

Page 40: ...Installation Conditions 3 12 C141 E042 01EN Figure 3 14 Example 2 of Cable Select ...

Page 41: ...4 3 Circuit Configuration 4 4 Power on sequence 4 5 Self calibration 4 6 Read Write circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks ...

Page 42: ...ns the control circuits for the disk drive The disk drive has one PCA For details see Sections 4 3 4 2 1 Disk The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm The MHA2032 has three disks and MHA2021AT has two disks The head contacts the disk each time the disk rotation stops the life of the disk is 50 000 contacts or more Servo data is recorded on top disk Servo...

Page 43: ... edge of the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head 4 2 5 Air filter There are two types of air filters a breather filter and a circulation filter The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle ...

Page 44: ... encoder and decoder and servo demodulation circuit 2 Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processeing by a MPU and then reconverted to an analog signal for control of the voice coil motor The MPU precisely sets ea...

Page 45: ...4 3 Circuit Configuration C141 E042 01EN 4 5 Figure 4 2 Circuit Configuration ...

Page 46: ...is data buffer read write test after enabling response to the ATA bus c After confirming that the spindle motor has reached rated speed the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM This unlocks the heads which are parked at the inner circumference of the disks d The disk drive positions the heads onto the SA area and reads out the system ...

Page 47: ... 1 Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution The torque vary with the disk drive and the cylinder where the head is positioned To execute stable fast seek operations external forces are occasionally sensed The firmware of the drive measures and stores the force value of the actuator motor drive current...

Page 48: ...op gain from the position signal and stores the compensation value against to the target gain as ratio For compensating the direction current value to the power amplifier is multiplied by the compensation value By this compensation loop gain becomes constant value and the stable servo control is realized To compensate torque constant value change depending on cylinder whole cylinders from most inn...

Page 49: ...rite service is necessary the disk drive positions the head to the track requested by the host reads or writes data and restarts calibration This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 100 ms 4 6 Read write Circuit The read write circuit consists of the read wri...

Page 50: ...sent to the PreAMP and the data is written onto the media 1 8 9 GCR The disk drive converts data using the 8 9 0 4 4 group coded recording GCR algorithm This code format is 0 to 4 code bit 0 s are placed between 1 s 2 Write precompensation Write precompensation compensates during a write process for write non leneartiry generated at reading Table 4 2 shows the write precompensation algorithm Table...

Page 51: ...4 6 Read write Circuit C141 E042 01EN 4 11 Figure 4 4 Read write circuit block diagram ...

Page 52: ...t fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut off frequency of the low pass filter and boost up gain are controlled from each DAC circuit...

Page 53: ...ding data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant The drive divides data area into 13 zones to set the data transfer rate Table 4 3 describes the data transfer rate and recording density BPI...

Page 54: ...according to the servo data that is written on the data side beforehand 4 7 1 Servo control circuit Figure 4 6 is the block diagram of the servo control circuit The following describes the functions of the blocks Figure 4 6 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU includes the AD converter and DSP unit etc and the MPU starts the spindle motor moves the heads to the ...

Page 55: ...d to reference cylinder Drives the VCM to position the head at the any cylinder in the data area The logical initial cylinder is at the outermost circumference cylinder 0 c Seek to specified cylinder Drives the VCM to position the head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration valu...

Page 56: ...Theory of Device Operation 4 16 C141 E042 01EN Figure 4 7 Physical sector servo configuration on disk surface ...

Page 57: ...gnals converts them to digital and transfers the digital signal to the DSP unit 4 D A converter DAC The D A converter DAC converts the VCM drive current value digital value calculated by the DSP unit into analog values and transfers them to the power amplifier 5 Power amplifier The power amplifier feeds currents corresponding to the DAC output signal voltage to the VCM 6 Spindle motor control circ...

Page 58: ...ea SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving 4 7 3 Servo frame format As the servo information the IDD uses the two phase servo generated from the gray code and servo A to D This servo information is used for positioning operation of radius direction and pos...

Page 59: ...The MPU fetches the position sense data on the servo frame at a constant interval of sampling time executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the seek operation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the t...

Page 60: ...ference between the target position and the position clarified by the detected position sense data The filtering includes servo compensation These are digitally controlled by the firmware 4 7 5 Spindle motor control Hall less three phase twelve pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC herea...

Page 61: ... SVC and accelerates till the rotational speed reaches 4 000 rpm When the rotational speed reaches 4 000 rpm the SVC enters the stable rotation mode 3 Stable rotation mode The MPU calcurates a time for one revolution of the spindle motor based on the PHASE signal from the SVC The MPU takes a difference between the current time and a time for one revolution at 4 000 rpm that the MPU already recogni...

Page 62: ... 01EN 5 1 CHAPTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Timing This chapter gives details about the interface and the interface commands and timings ...

Page 63: ...01EN 5 1 Physical Interface 5 1 1 Interface signals Figure 5 1 shows the interface signals Figure 5 1 Interface signals 5 1 2 Signal assignment on the connector Table 5 1 shows the signal assignment on the interface connector ...

Page 64: ... INTRQ DA1 DA0 CS0 DASP 5 VDC GND B D F 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 GND MSTR KEY GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 KEY GND GND GND CSEL GND IOCS16 PDIAG DA2 CS1 GND 5 VDC unused signal I O Description ENCSEL I This signal is used to set master slave using the CSEL signal pin 28 Pins A and C Open Sets master slave by the MSTR signal without ...

Page 65: ...ses assertion of RESET signal Reset by SRST of the Device Control register Write to the command register by the host Read of the status register by the host Completion of sector data transfer without reading the Status register The signal output line has a high impedance when no devices are selected or interruption is disabled IOCS16 O This signal indicates 16 bit data bus is addressed in PIO data...

Page 66: ... pulled up with 240 kΩ resistor DMACK I The host system asserts this signal as a response that the host system receive data or to indicate that data is valid DMARQ O This signal is used for DMA transfer between the host system and the device The device asserts this signal when the device completes the preparation of DMA data transfer to the host system at reading or from the host system at writing...

Page 67: ...d Sector Number registers are LBA bits The sector No under the LBA mode proceeds in the ascending order with the start point of LBA0 defined as follows LBA0 Cylinder 0 Head 0 Sector 1 Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command the sector LBA address is not changed LBA Cylinder No Number of head Head No Number of sector track Sector No ...

Page 68: ...valid Invalid Control block registers H L H H L Alternate Status Device Control X 3F6 H L H H H X 3F7 Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATA0 to DATA15 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus DATA0 to DATA7 3 When reading the Drive Address register bit 7 is high impedance stat...

Page 69: ...d Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICRC UNC X IDNF X ABRT TK0NF X X Unused Bit 7 Interface CRC Error ICRC This bit indicates that a CRC error occurred during Ultra DMA transfer Bit 6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error except for bad sector uncorrectable...

Page 70: ...read or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 When this register indicates X 00 at the completion of the command execution this indicates that the command is completed succefully If the command is not completed scuccessfully this register indicates the number of sectors to be transferred to complete the request from t...

Page 71: ...e high order 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 8 Device Head register X 1F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit ...

Page 72: ...stem should not write the command block registers If the host system reads any command block register when BSY bit is 1 the contents of the Status register are posted This bit is set by the device under following conditions a Within 400 ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit i...

Page 73: ...the host system and the device Bit 2 Corrected Data CORR bit This bit indicates that a correctable data error was encountered and the error has been corrected This condition does not halt the data transfer Bit 1 Always 0 Bit 0 Error ERR bit This bit indicates that an error was detected while the previous command was being executed The Error register indicates the additional information of the caus...

Page 74: ... the device is held reset state When two device are daisy chained on the interface setting this bit resets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this...

Page 75: ... Y Y Y Y READ VERIFY SECTOR S 0 1 0 0 0 0 0 R N Y Y Y Y WRITE MULTIPLE 1 1 0 0 0 1 0 1 N Y Y Y Y WRITE DMA 1 1 0 0 1 0 1 R N Y Y Y Y WRITE VERIFY 0 0 1 1 1 1 0 0 N Y Y Y Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y RECALIBRATE 0 0 0 1 X X X X N N N N D SEEK 0 1 1 1 X X X X N N Y Y Y INITIALIZE DEVICE PARAMETERS 1 0 0 1 0 0 0 1 N Y N N Y IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1...

Page 76: ... MODE 1 1 0 1 0 1 1 0 1 0 0 1 0 0 0 1 N N N N D SMART 1 0 1 1 0 0 0 0 Y Y Y Y D SECURITY DISABLE PASSWORD 1 1 1 1 0 1 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N N D SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D Notes FR Features Register CY Cylind...

Page 77: ...ndication of the I O registers at command conpletion are shown as following in this subsection Example READ SECTOR S WITH RETRY At command issuance I O registers setting contents Bit 7 6 5 4 3 2 1 0 1F7H CM 0 0 1 0 0 0 0 0 1F6H DH L DV Head No LBA MSB 1F5H CH Start cylinder address MSB LBA 1F4H CL Start cylinder address LSB LBA 1F3H SN Start sector No LBA LSB 1F2H SC Transfer sector count 1F1H FR ...

Page 78: ...fied in the Device Head Cylinder High Cylinder Low and Sector Number registers Number of sectors can be specified to 256 sectors in maximum To specify 256 sectors reading 00 is specified For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 1 If the head is not on the track specified by the host the device performs a implied seek After the head reaches to the specified tr...

Page 79: ...R 0 with Retry R 1 without Retry At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV End head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is se...

Page 80: ...d evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled the ...

Page 81: ...Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV End head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of secto...

Page 82: ...signal and posts a status to the host system The format of the error information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not transferred like in the CHS mode are ...

Page 83: ...ll requested sectors are verified the device clears the BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain the cylinder head and sector number of the last sector verified If an error occurs the verify operation is terminated at the sector where the error occurred The command block registers contain the cylinder...

Page 84: ... due to an error the remaining number of sectors of which data was not transferred is set in this register 5 WRITE SECTOR S X 30 or X 31 This command writes data of sectors from the address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers to the address specified in the Sector Count register Number of sectors can be specified to 256 sectors in maximum Data transf...

Page 85: ...Then the host can read the command block registers to determine what error has occurred and on which sector the error has occurred At command issuance I O registers setting contents 1F7H CM 0 0 1 1 0 0 0 R 1F6H DH L DV Start head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx R 0 with Retry R 1...

Page 86: ...nd even if the value of the Sector Count register is less than the defined block count the value of the Sector Count should not be 0 If the number of requested sectors is not divided evenly having the same number of sectors block count as many full blocks as possible are transferred then a final partial block is transferred The number of sectors in the partial block to be transferred is n where n ...

Page 87: ...OR S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device The device posts a status as the result of command execution only once at...

Page 88: ... command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV End head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 8 WRITE VERIFY X...

Page 89: ...rmation 1F6H DH L DV End head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 9 RECALIBRATE X 1x x X 0 to X F This command performs the calibration Upon receipt of thi...

Page 90: ...formation Note Also executable in LBA mode 10 SEEK X 7x x X 0 to X F This command performs a seek operation to the track and selects the head specified in the command block registers After completing the seek operation the device clears the BSY bit in the Status register and generates an interrupt The IDD always sets the DSC bit Drive Seek Complete status of the Status register to 1 In the LBA mod...

Page 91: ...h this command Upon receipt of this command the device sets the BSY bit of Status register and saves the parameters Then the device clears the BSY bit and generates an interrupt When the SC register is specified to X 00 an ABORTED COMMAND error is posted Other than X 00 is specified this command terminates normally The parameters set by this command are retained even after reset or power save oper...

Page 92: ... xx Number of sectors track Error infomation 12 IDENTIFY DEVICE X EC The host system issues the IDENTIFY DEVICE command to read parameter information 512 bytes from the device Upon receipt of this command the drive sets the BSY bit of Status register and sets required parameter information in the sector buffer The device then sets the DRQ bit of the Status register and generates an interrupt After...

Page 93: ...H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information Table 5 4 Information to be read by IDENTIFY DEVICE command 1 of 3 Word Value Description 0 X 0c5a General Configuration 1 1 X 1068 X 189C Number of cylinders MHA2021AT X 1068 MHA2032AT X 189C 2 X 0000 Reserved 3 X 0010 Number of Heads 4 X 0000 Undefined 5 X 0000 Undefined 6 X 003F Number of sectors per track 7 9 X 000000000000 Und...

Page 94: ...ent Head 56 Variable Number of current sectors per track 57 58 Variable Total number of current sectors 59 8 Transfer sector count currently set by READ WRITE MULTIPLE command 8 60 61 X 00409980 X 0060E640 Total number of user addressable sectors LBA mode only MHA2021AT X 00409980 MHA2032AT X 0060E640 62 X 0000 Reserved 63 X xx07 Multiword DMA transfer mode 9 64 X 0003 Advance PIO transfer mode su...

Page 95: ...ice 0 ATAPI device 1 0 Bit 14 12 Undefined 0 Bit 11 Rotational speed tolerance is more than 0 5 1 Bit 10 Disk data transfer rate 10 Mbps 1 Bit 9 Disk data transfer rate is faster than 5 Mbps but 10 Mbps or slower 0 Bit 8 Disk data transfer rate is 5 Mbps or slower 0 Bit 7 Removable disk drive 0 Bit 6 Fixed drive 1 Bit 5 Spindle motor control option implemented 0 Bit 4 Head switching time is more t...

Page 96: ... Bit 7 0 Undefined 6 Word 51 PIO data transfer mode Bit 15 8 PIO data transfer mode X 02 PIO mode 2 Bit 7 0 Undefined 7 Word 53 Enable disable setting of word 54 58 and 64 70 Bit 15 3 Reserved Bit 2 Enable disable setting of word 88 1 Enable Bit 1 Enable disable setting of word 64 70 1 Enable Bit 0 Enable disable setting of word 54 58 1 Enable 8 Word 59 Transfer sector count currently set by READ ...

Page 97: ...tatus Bit 15 8 Reserved Bit 7 0 Advance PIO transfer mode Bit 1 1 Mode 4 Bit 0 1 Mode 3 11 WORD 80 Bit 15 4 Reserved Bit 3 ATA 3 supported 1 Bit 2 ATA 2 supported 1 Bit 1 ATA 1 supported 1 Bit 0 Undefined 12 WORD 82 Bit 15 4 Reserved Bit 3 Power Management feature set supported 1 Bit 2 Removable feature set supported 0 Bit 1 Security feature set supported 1 Bit 0 SMART feature set supported 1 13 W...

Page 98: ...IDENTIFY DEVICE DMA X EE When this command is not used to transfer data to the host in DMA mode this command functions in the same way as the Identify Device command At command issuance I O registers setting contents 1F7H CM 1 1 1 0 1 1 1 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH...

Page 99: ... Features register Table 5 5 Features register values and settable modes Features Register Drive operation mode X 02 Enables the write cache function X 03 Transfer mode depends on the contents of the Sector Count register Details are given later X 55 Disables read cache function X 66 Disables the reverting to power on default settings after software reset X 82 Disables the write cache function X A...

Page 100: ...egister By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND error is posted PIO default transfer mod...

Page 101: ...unts Upon receipt of this command the device sets the BSY bit of the Status register and checks the contents of the Sector Count register If the contents of the Sector Count register is valid and is a supported block count the value is stored for all subsequent READ MULTIPLE and WRITE MULTIPLE commands Execution of these commands is then enabled If the value of the Sector Count register is not a s...

Page 102: ... After power on or after hardware reset the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode The mode established before software reset is retained if disable default Features Reg 66h setting has been defined by the SET FEATURES command If disable default has not been defined after the software is the READ MULTIPLE and WRITE MULTIPLE commands are disabled The par...

Page 103: ...gnosis If device 1 is present Both devices shall execute self diagnosis The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG signal If the device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 80 to its own diagnostic status The device 0 clears the BSY bit of the Status register and generates an interrupt The device 1 does not generate an i...

Page 104: ...0 1F6H DH DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx 01H 1 01H Diagnostic code 1 This register indicates X 00 in the LBA mode 17 READ LONG X 22 or X 23 This command operates similarly to the READ SECTOR S command ...

Page 105: ...t command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error this register indicates 01 18 WRITE LONG X 32 or X 33 This command operates similarly to the READ SECTOR S command except...

Page 106: ...with Retry R 1 without Retry At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error this register indicates 01 19 READ BUFFER X E4 The host system can read the current content...

Page 107: ...xx xx xx Error information 20 WRITE BUFFER X E8 The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command Upon receipt of this command the device sets the BSY bit of the Status register Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data After that 512 bytes o...

Page 108: ...evice is already rotating the spin up sequence shall not be implemented By using this command the automatic power down function is enabled and the timer immediately starts the countdown When the timer reaches the specified value the device enters standby mode Enabling the automatic power down function means that the device automatically enters the standby mode after a certain period of time When t...

Page 109: ...5 X FE to X FF 21 minutes 15 seconds attention The automatic power down is excuted if no command is coming for 30 min default At command issuance I O registers setting contents 1F7H CM X 97 or X E3 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx Period of timer xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN...

Page 110: ...7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information 23 STANDBY X 96 or X E2 Upon receipt of this command the device sets the BSY bit of the Status register and enters the standby mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the standby mode If th...

Page 111: ... setting contents 1F7H CM X 96 or X E2 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx Period of timer xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information 24 STANDBY IMMEDIATE X 94 or X E0 Upon receipt of this command the device sets the BSY bit of the Status registe...

Page 112: ... E6 This command is the only way to make the device enter the sleep mode Upon receipt of this command the device sets the BSY bit of the Status register and enters the sleep mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface ...

Page 113: ...information 26 CHECK POWER MODE X 98 or X E5 The host checks the power mode of the device with this command The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers The device sets the BSY bit and sets the following register value After that the device clears the BSY bit and generates an interrupt Power save mode Sector Count ...

Page 114: ...fied in the FR register is supported the Aborted Command error is posted It is necessary for the host to set the keys CL 4Fh and CH C2h in the CL and CH registers prior to issuing this command If the keys are set incorrectly the Aborted Command error is posted In the default setting the failure prediction feature is disabled In this case the Aborted Command error is posted in response to subcomman...

Page 115: ...urned off and then on When the automatic saving feature is enabled the attribute values are saved before the device enters the power saving mode However if the failure prediction feature is disabled the attribute values are not automatically saved When the device receives this subcommand it asserts the BSY bit enables or disables the automatic saving feature then clears the BSY bit X D3 SMART Save...

Page 116: ...egister D0h SMART Save Attribute Values subcommand FR register D3h or SMART Return Status subcommand FR register DAh to save the device attribute value data on a medium Alternative the device must issue the SMART Enable Disable Attribute AutoSave subcommand FR register D2h to use a feature which regularly save the device attribute value data to a medium The host can predict failures in the device ...

Page 117: ...ailure threshold value data is 512 byte data the format of this data is shown below The host can access this data using the SMART Read Attribute Thresholds subcommand FR register D1h Table 5 8 Format of device attribute value data Byte Item 00 01 Data format version number 02 Attribute 1 Attribute ID 03 04 Status flag 05 Current attribute value 06 Attribute value for worst case so far 07 to 0C Raw...

Page 118: ...Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds The data format version numbers of the device attribute values and insurance failure thresholds are the same When a data format is changed the data format version numbers are updated Attribute ID The attribute ID is defined as foll...

Page 119: ...ue gets to 01h the higher the possibility of a failure The device compares the attribute values with thresholds When the attribute values are larger than the thresholds the device is operating normally Attribute value for the worst case so far This is the worst attribute value among the attribute values collected to date This value indicates the state nearest to a failure so far Raw attribute valu...

Page 120: ... passwords are the same Although this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while in LOCKED MODE or FROZEN MODE returns the Abort...

Page 121: ...6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information 29 SECURITY ERASE PREPARE F3h The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command Issuing this command during FROZEN...

Page 122: ... 512 byte data shown in Table 1 1 to the device The device compares the user password or master password in the transferred data with the user password or master password already set The device erases user data invalidates the user password and releases the lock function if the passwords are the same Although this command invalidates the user password the master password is retained To recover the...

Page 123: ... the device into FROZEN MODE The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE SECURITY SET PASSWORD SECURITY UNLOCK SECURITY DISABLE PASSWORD SECURITY ERASE UNIT FROZEN MODE is canceled when the power is turned off If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged Issuing thi...

Page 124: ...LE SECURITY SET PASSWORD READ SECTORS WRITE SECTORS WRITE VETIF At command issuance I O register contents 1F7H CM 1 1 1 1 0 1 0 1 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O register contents 1F7H CM Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information ...

Page 125: ...ing to the specifications of the Identifier bit and Security level bit in the transferred data Table 1 3 Issuing this command in LOCKED MODE or FROZEN MODE returns the Aborted Command error Table 5 11 Contents of SECURITY SET PASSWORD data Word Contents 0 Control word Bit 0 Identifier 0 Sets a user password 1 Sets a master password Bits 1 to 7 Reserved Bit 8 Security level 0 High 1 Maximum Bits 9 ...

Page 126: ...lock function is not enabled User Maximum The specified password is saved as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password only The master password already set cannot cancel LOCKED MODE Master Maximum The specified password is saved as a new master password The lock function is not enabled At command ...

Page 127: ...When the user password is selected The password is compared with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the UNLOCK counter reaches zero this command or the SECURITY E...

Page 128: ...ters 1 of 2 Command name Error register X 1F1 Status register X 1F7 BBK UNC INDF ABRT TK0NF DRDY DWF CORR ERR READ SECTOR S V V V V V V V V WRITE SECTOR S V V V V V V READ MULTIPLE V V V V V V V V WRITE MULTIPLE V V V V V V READ DMA V V V V V V V V WRITE DMA V V V V V V WRITE VERIFY V V V V V V V V READ VERIFY SECTOR S V V V V V V V V RECALIBRATE V V V V V SEEK V V V V V INITIALIZE DEVICE PARAMETE...

Page 129: ... READ LONG V V V V V V V WRITE LONG V V V V V V READ BUFFER V V V V WRITE BUFFER V V V V IDLE V V V V IDLE IMMEDIATE V V V V STANDBY V V V V STANDBY IMMEDIATE V V V V SLEEP V V V V CHECK POWER MODE V V V V SMART V V V V V SECURITY DISABLE PASSWORD V V V V SECURITY ERASE PREPARE V V V V SECURITY ERASE UNIT V V V V SECURITY FREEZE LOCK V V V V SECURITY SET PASSWORD V V V V Invalid command V V V V V ...

Page 130: ...D LONG command 516 bytes are transferred Following shows the protocol outline a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector of data is available for transfer to the ho...

Page 131: ... example protocol for command abort Figure 5 3 Read Sector s command protocol Note For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the device to 50 ms after the completion of the sector data transfer Note that the host does not need to read the Status re...

Page 132: ...a transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive WRITE SECTOR S WRITE LONG WRITE BUFFER WRITE VERIFY SECURITY DISABLE PASSWORD SECURITY ERASE UNIT SECURITY SET PASSWORD SECURITY UNCLOK The execution of these commands includes the transfer one or more sectors of data from the host to the device In the WRITE LONG co...

Page 133: ...rs the DRQ bit and sets the BSY bit f When the drive completes transferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive sets the DRQ bit g After detecting the INTRQ signal assertion the host reads the Status register h The device resets INTRQ the interrupt signal I If transfer of another sector is requested steps d ...

Page 134: ...tion is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not guaranteed 5 4 3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device RECABLIBRATE SEEK READY VERIFY SECTOR S EXECUTE DEVICE DI...

Page 135: ...ransfer differs the following point The interrupt processing for the DMA transfer differs the following point a The host writes any parameters to the Features Sector Count Sector Number Cylinder and Device Head register b The host initializes the DMA channel c The host writes a command code in the Command register d The device sets the BSY bit of the Status register e The device asserts the DMARQ ...

Page 136: ...5 4 Command Protocol C141 E042 01EN 5 75 Figure 5 7 Normal DMA data transfer ...

Page 137: ...Interface 5 76 C141 E042 01EN 5 5 Timing 5 5 1 PIO data transfer Figure 5 8 shows of the data transfer timing between the device and the host system ...

Page 138: ...5 5 Timing C141 E042 01EN 5 77 Figure 5 8 Data transfer timing ...

Page 139: ...ce 5 78 C141 E042 01EN 5 5 2 Single word DMA data transfer Figure 5 9 show the single word DMA data transfer timing between the device and the host system Figure 5 9 Single word DMA data transfer timing mode 2 ...

Page 140: ... 5 10 shows the multiword DMA data transfer timing between the device and the host system Figure 5 10 Multiword DMA data transfer timing mode 2 5 5 4 Power on and reset Figure 5 11 shows power on and reset hardware and software reset timing 1 Only master device is present ...

Page 141: ...Interface 5 80 C141 E042 01EN 2 Master and slave devices are present 2 drives configulation Figure 5 11 Power on Reset Timing ...

Page 142: ...C141 E042 01EN 6 1 CHAPTER 6 Operations 6 1 Device Response to the Reset 6 2 Address Translation 6 3 Power Save 6 4 Defect Management 6 5 Read Ahead Cache 6 6 Write Cache ...

Page 143: ...recognizes presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has sucessfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own ...

Page 144: ...6 1 Device Response to the Reset C141 E042 01EN 6 3 Figure 6 1 Response to power on ...

Page 145: ...signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the self diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device receives the hardware reset the slave device shall report its presense and the result of the self diagnostic...

Page 146: ... completed the self diagnosis successfully After the slave device receives the software reset the slave device shall report its presense and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 15 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DAS...

Page 147: ...s successfully The master device does not check the DASP signal After the slave device receives the EXECUTE DEVICE DIAGNOSTIC command it shall report the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates...

Page 148: ...lled sa the default translation mode The parameters in Table 6 1 are called BIOS specification Table 6 1 Default parameters MHA2021AT MHA2032AT Number of cylinders 4 200 6 300 Number of heads 16 16 Number of sectors track 63 63 Formatted capacity MB 2 167 6 3 251 4 As long as the formatted capacity of the IDD does not exceed the value shown on Table 6 1 the host can freely specify the number of cy...

Page 149: ...f the last sector in a zone of a physical head is used the track is switched and the next logical sector is placed in the initial sector in the same zone of the subsequent physical head After the last physical sector of the last physical head is used in the zone the subsequent zone is used and logical sectors are assigned from physical head 0 in the same way Figure 6 5 shows an example of 4 heads ...

Page 150: ...is used and LBA is assigned from physical head 0 in the same way Figure 6 6 shows an example of 4 heads configuration assuming there is no track skew 431 216 215 214 215 216 216 215 430 218 217 216 Figure 6 6 Address translation example in LBA mode 6 3 Power Save The host can change the power consumption state of the device by issuing a power command to the device 6 3 1 Power save mode There are f...

Page 151: ...circuits on the device is set to power save mode The device enters the Idle mode under the following conditions After completion of power on sequence After completion of the command execution other than SLEEP and STANDBY commands After completion of the reset sequence 3 Standby mode In this mode the VCM circuit is turned off and the spindle motor is stopped The device can receive commands through ...

Page 152: ...urn from the standby mode is to execute a software or hardware reset The drive enters the sleep mode under the following condition A SLEEP command is issued Issued commands are invalid ignored in this mode 6 3 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE 6 4 Defect Management Defective sectors of which ...

Page 153: ...ds described below are available 1 Sector slip processing A defective sector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector physically adjacent sector to the defective sector When defective sector is present the sector slip processing is performed in the formatting Figure 6 7 shows an example where physical sector 5 is defective on head 0 in cyl...

Page 154: ...quest to physical sector 5 is specified the device accesses the alternated sector in the alternate cylinder instead of sector 5 When an access request to sectors next to sector 5 is specified the device seeks to cylinder 0 head 0 and continues the processing 3 Automatic alternate assignment The device performs the automatic alternate assignment when ECC correction performance is increased during r...

Page 155: ...6 9 Data buffer configuration The read ahead operation is performed at execution of the READ SECTOR S READ MULTIPLE or READ DMA command and read ahead data is stored in the buffer for read commands However the lead sector specified in the read command is continued to the last sector specified in the previous read command the read ahead operation is not performed 6 5 2 Caching operation Caching ope...

Page 156: ...e data However since the hit check at issurance of read command is performed to the data buffer for read command prioritily caching write data is limited to the case that the hit check is missed at the data buffer for read command When all data requested by the read command are stored in the data buffer for write command hit all the device transfers data from the data buffer for write command At t...

Page 157: ...te command is issued write data kept until now are invalidated 6 5 3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases 1 Mis hit no hit A lead block of the read requested data is not stored in the data buffer The requested data is read from the disk media The read ahead operation is performed only when the last sector address of the previous rea...

Page 158: ...ped HAP 4 Following shows the cache enabled data for next read command Cache enabled data Empty area 2 Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command the disk drive starts the read ahead operation a Sequential command just after non sequential command When the previously executed read command is an non sequential comma...

Page 159: ...ing the requested data Requested data DAP HAP Mis hit data Empty area 3 After completion of the reading and transferring the requested data to the host system the disk drive performs the read ahead operation continuously Requested data DAP HAP Completion of transferring requested data Empty area Read ahead data 4 The disk drive performs the read ahead operation for all area of segment with overwri...

Page 160: ...he same time as the disk drive starts transferring data to the host system 1 In the case that the contents of buffer is as follows at receiving a read command Start LBA Last LBA DAP HAP Continued from the previous read request data Hit data Read ahead data 2 The disk drive starts the read ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive star...

Page 161: ...e read ahead operation 1 In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command the disk drive sets the HAP to the address of which the hit data is stored HAP set to hit position for data transfer Last position at previous read command Last position at previous read command Cache data Full hit data Cache data 2 The disk driv...

Page 162: ...s an example of partially hit to the cache data Last LBA Cache data 1 The disk drive sets the HAP to the address where the partially hit data is stored and sets the DAP to the address just after the partially hit data HAP DAP Partially hit data Lack data 2 The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time However the disk drive does not ...

Page 163: ... a target sector of the next command is eliminated This shortens the access time The drive generates an interrupt of command complete after completion of data transfer requested by the host system as same as at previous command When the write operation of the previous command had been completed the latency time occurs to search the target sector If the received command is not a sequential write th...

Page 164: ...6 6 Write Cache C141 E042 01EN 6 23 WRITE SECTOR S WITH RETRY WRITE MULTIPLE WRITE DMA WITH RETRY ...

Page 165: ... The physical specifications of the drive do not always correspond to these parameters The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command ...

Page 166: ...e spindle motor is stopped and circuits other than the interface control circuit are sleeping The drive enters sleep mode when the host issues the SLEEP command Reserved Reserved bits bytes and fields are set to zero and unusable because they are reserved for future standards Rotational delay Time delay due to disk rotation The mean delay is the time required for half a disk rotation The mean dela...

Page 167: ...rmation posted from the drive to the host when command execution is ended The status indicates the command termination state VCM Voice coil motor The voice coil motor is excited by one or more magnets In this drive the VCM is used to position the heads accurately and quickly ...

Page 168: ...ter DRDY Drive ready DRQ Ddata request bit DSC Drive seek complete DWF Drive write fault E ECC Error checking and correction ER Error register ERR Error F FR Feature register H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programed i...

Page 169: ... 13 Average positioning time 1 2 B Block diagram read write circuit 4 11 Block diagram of servo control circuit 4 14 Blower 4 3 Blower effect 2 4 Breather filter 4 3 BSY 5 11 Buffer data 1 3 C Cable connection 3 7 3 8 Cable connector specification 3 8 Cache write 1 3 Cache system read ahead 1 3 Caching operation 6 14 Calibration 4 15 Carriage head 4 3 CHECK POWER MODE 5 52 Check sum 5 58 CHS mode ...

Page 170: ...ion 1 6 Current fluctuation when power is turned on 1 6 Current requirement 1 6 Cylinder High register 5 10 Cylinder Low register 5 10 D DAC 4 17 D A converter 4 17 Data object of caching operation 6 15 Data area 4 18 Data assurance in event of power failure 1 9 Data buffer 1 3 Data buffer configuration 6 14 Data corruption 3 6 Data format version number 5 57 Data register 5 8 Data separator circu...

Page 171: ...rformance 1 2 G Gray code 4 19 Guard band inner 4 18 Guard band outer 4 18 H HA 2 5 Head 2 2 4 2 Head carriage 4 3 Head structure 4 3 High speed transfer rate 1 2 Hit full 6 20 Hit no 6 16 Hit partially 6 21 Hit sequential 6 19 Hit all 6 20 Host command 5 13 I ID attribute 5 57 IDENTIFY DEVICE 5 31 IDENTIFY DEVICE DMA 5 37 IDLE 5 47 IDLE IMMEDIATE 5 49 Idle mode 6 10 INITIALIZE DEVICE PARAMETERS 5...

Page 172: ...ata transfer 5 76 PIO Mode 4 2 4 Positioning error 1 9 Power amplifier 4 17 Power commands 6 11 Power dissipation 1 6 Power on 5 79 Power on off sequence 1 6 Power on sequence 4 6 Power on timing 5 80 Power requirement 1 5 Power save 6 9 Power save mode 1 2 6 9 Power supply connector 3 9 PreAMP 4 9 Processing command 4 9 Processing sector slip 16 12 Product number model name 1 5 Programmable filte...

Page 173: ...4 19 Servo burst capture 4 17 Servo burst capture circuit 4 17 Servo C 4 19 Servo circuit 4 4 Servo control 4 14 Servo control circuit 4 14 Servo D 4 19 Servo format data surface 4 18 Servo frame format 4 18 Servo mark 4 19 SET FEATURES 5 38 SET MULTIPLE MODE 5 40 Setting CSEL 3 11 Setting factory default 3 10 Setting jumper 3 9 Setting master drive 3 10 Setting slave drive 3 10 Shock 1 8 Signal i...

Page 174: ...iword DMA data transfer 5 79 Timing power 5 80 Timing reset 5 80 Timing single word DMA data transfer 5 78 Track following operation 4 20 Transfer rate data 4 13 U Translation address 6 7 6 8 Unrecoverable read error 1 9 Usage of read segment 6 16 User password 5 66 V VCM 4 3 VCM current sense resistor CSR 4 17 Vibration 1 8 Viterbi detection circuit 4 13 Voice coil motor 4 3 W WRITE BUFFER 5 46 W...

Page 175: ...P Poor General appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 22 7 Minami Ooi 6 Chome Shinagawa Ku Tokyo 140 JAPAN F...

Page 176: ...MHA2021AT MHA2032AT DISK DRIVES PRODUCT MANUAL C141 E042 01EN MHA2021AT MHA2032AT DISK DRIVES PRODUCT MANUAL C141 E042 01EN ...

Page 177: ......

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