4.6 Read/write Circuit
C141-E042-01EN
4-9
Table 4.1 Self-calibration execution timechart
Time elapsed
Time elapsed
(accumulated)
1
At power-on
Initial calibration
2
About 5 minutes
About 5 minutes
3
About 5 minutes
About 10 minutes
4
About 10 minutes
About 20 minutes
5
About 10 minutes
About 30 minutes
6
About 15 minutes
About 45 minutes
7
About 15 minutes
About 60 minutes
8
.
.
.
.
Every about 30
minutes
4.5.3 Command processing during self-calibration
If the disk drive receives a command execution request from the host while
executing self-calibration according to the timechart, the disk drive terminates
self-calibration and starts executing the command precedingly. In other words, if
a disk read or write service is necessary, the disk drive positions the head to the
track requested by the host, reads or writes data, and restarts calibration.
This enables the host to execute the command without waiting for a long time,
even when the disk drive is performing self-calibration. The command execution
wait time is about maximum 100 ms.
4.6 Read/write Circuit
The read/write circuit consists of the read/write preamplifier (PreAMP), the write
circuit, the read circuit, and the time base generator in the read channel (RDC).
Figure 4.4 is a block diagram of the read/write circuit.
4.6.1 Read/write preamplifier (PreAMP)
One PreAMP is mounted on the FPC. The PreAMP consists of an read
preamplifier and a write current switch and senses a write error. Each channel is
connected to each data head. The head IC switches the heads by the chip select
signals (*CS) and the head select signals. The IC generates a write error sense
Summary of Contents for MHA2021AT
Page 1: ...C141 E042 01EN MHA2021AT MHA2032AT DISK DRIVES PRODUCT MANUAL ...
Page 40: ...Installation Conditions 3 12 C141 E042 01EN Figure 3 14 Example 2 of Cable Select ...
Page 45: ...4 3 Circuit Configuration C141 E042 01EN 4 5 Figure 4 2 Circuit Configuration ...
Page 51: ...4 6 Read write Circuit C141 E042 01EN 4 11 Figure 4 4 Read write circuit block diagram ...
Page 136: ...5 4 Command Protocol C141 E042 01EN 5 75 Figure 5 7 Normal DMA data transfer ...
Page 138: ...5 5 Timing C141 E042 01EN 5 77 Figure 5 8 Data transfer timing ...
Page 144: ...6 1 Device Response to the Reset C141 E042 01EN 6 3 Figure 6 1 Response to power on ...
Page 177: ......