LAP-F1 Logic Analyzer
|
User Guide v1.6
| www.zeroplus.com.tw
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Protocol Triggers (HW)
I2C, I2S, SPC, SVID, UART, CAN2.0B
eMMC trigger
4 channels only; see Special functions below for full
support
Software functions
Languages
English, Chinese (Traditional), Chinese (Simplified)
Zooming & Panning
Two cursor modes
Wavefrom & UI
customization
Modify the appearance of channels, menus, traces,
windows etc
State List & Waveform View
Present the samples as a list of 1s and 0s or as a
waveform
DSO Connection
Connect to and import signals from DSOs
Files Comparison
Compare 2 files to quickly see where and how they differ
Navigator
Instantly navigate to distant parts of the waveform
Memory View
See what the memory looks like; what is read/written to
each address
Packet List
Breakdown of all packets in list form
Statistics
Table view of number of periods, periods that satisfy
conditions etc
Find Results
Set conditions, look up the information meets the
requirements
eMMC Decoder
Decode 4 eMMC signals for free
Real-time Signal Activity
Live view of probe activity
Protocol Decoders
More than 110 free, built-in protocol decoders
Miscellaneous
Phase Errors
< 3 ns
Power
AC (IN): 100-240 V 50/60 Hz; DC (OUT): 9 V / 5.55 A
Dimensions
322 x 180 x 38 mm
Special Functions (Optional) See chapter 1.6.4.
Certifications
CE and FCC
Table 1:4 LAP-F1 specifications
1.6.3.
Available Models
Model
Channels
Memory depths available
LAP-F1 40
4, 8, 16, 32 and 64 Mb/channel
LAP-F1 64
4, 8, 16, 32 and 64 Mb/channel