LAP-F1 Logic Analyzer
|
User Guide v1.6
| www.zeroplus.com.tw
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sample on rising or falling DUT clocks, or on either. The State mode
sample rate goes from 0.001 Hz to 200 MHz.
Timing (Internal
Clock)
In Timing mode (also called asynchronous acquisition) the input
signals are sampled and stored at equal time intervals based on
LAP-F1’s internal clock. The Timing mode sample rate goes from 5
MHz to 1 GHz.
Acquisition Choices
Sample Depth
Determine the amount of data to be acquired per channel; it is set to
32 k by default. The number below (highlighted in red in Figure
4-20) shows how long the acquisition will be.
Sample Rate
The sample rate or acquisition frequency determines how often
samples are taken. Press CTRL + U to increase the sample rate and
CTRL + D to decrease it.
Channel Selection
(Purple
checkboxes)
One probe is connected to each of the channel ports of the LAP-F1
and each probe samples one signal. By default, Port A0 (Probe0) is
linked with channel A0 in the software etc. Channels can be renamed
and rearranged: The left column shows the channel name in
ZP-Logic and the purple coloring determines which of the
ports/probes is linked to the channel.
Add Signal
Add a channel. The user must define which probe the new channel
should be linked to; by default it’s unassigned.
Delete Signal
Delete the selected channel.
Delete All
Delete all channels.
Trigger Level
See chapter 4.20.
DSO Connection
Set up a DSO Connection; see chapter 4.36.
Table 4:16 Acquisition Setup dialog box description
4.17.1.
Trigger Level
The Trigger Level defines when a signal changes state. In other words; if the voltage
of a signal is inferior to the Trigger Level it will be regarded as 0 (Low), and vice
versa. Similarly, when the signal voltage rises from below to above the Trigger Level,
the LAP-F1 will consider that a change of state from Low to High has occurred and
