A
1
2
3
4
5
6
7
8
9
10
BCD
E
F
G
H
I
J
K
L
M
N
YSP-4100/YSP-5100
92
MAIN 4/4
★
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
●
電圧は、内部抵抗
10MΩの電圧計で測定したものです。
●
⚠印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、
パーツリストに記載されている部品を使用してください。
●
本回路図は標準回路図です。改良のため予告なく変更することがございます。
REFERENCE
VOLTAGE
CIN
FLOUT
VREF
VREF
ANTIALIASING
FILTER
57kHz
BPF
(SCF)
SMOOTHING
FILTER
MPXIN
+3V
Vdda
Vssa
PLL
(57kHz)
CLOCK
RECOVERY
(1187.5Hz)
+3V
Vddd
RDS-ID/
READY
RST
Vssd
DATA
DECODER
XOUT
XIN
TEST
TEST
CLK(4.332MHz)
OSC
RAM
(128bits)
RDDA
RDCL
RDS-ID
DETECT
MODE
IC41
7
:
LC72725KM-UY
-TLM-E
RDS signal demodulation IC
CIN
TES
T
Vssd
MODE
Vddd
XIN
X
OUT
RS
T
RDCL
FL
OUT
RDS-ID/READ
Y
RDD
A
VREF
MPXIN
Vdda
Vssa
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
IC412
: MB90050PF-G-118-E1
OSD controller
IC412
: MB90050PF-G-119-E1
OSD controller
VOUT
YOUT
COUT
PO3
PO2
PO1
PO0
SIN
SCLK
CS
VIN
YIN
CIN
VSYNCI
FLDI
SYNCST
HSYNCI
HSYNCO
VSYNCO
CSYNCO
FLDO
VBLKO
EXS
XS
FSC4O
EXD
XD
DCLKO
BUSY
RESET
DCOL5 to DCOL0
DB
DH
Serial input
control
Analog
switch
Sync control
Video signal
generator circuit
NTSC/PAL
signal
generator
circuit
Output control
Palette
(4 bits 6 bits)
Display Memory control
Font RAM
(8 characters)
Font ROM
(512 characters)
VRAM
(35 characters
x 16 lines)
4FSC clock
oscillation
circuit
Dot clock
oscillation
circuit
Port control
Each block
Each block
All reset
Each block
FLDI
VSYNCI
HSYNCI
V
CC
V
SS
EXS
XS
FSC4O
VSYNCO
HSYNCO
CSYNCO
VBLK
O
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
PO3
PO2
DCOL5
DCOL4
DCOL3
DCOL2
DCOL1
DCOL0
DCLK
O
DB
DH
RESET
48
47
46
45
44
43
42
41
40
39
38
37
YOUT
TESTI2
YIN
AVSS2
CIN
AVCC2
COUT
AVSS1
VOUT
AVCC1
VIN
TESTI1
13
14
15
16
17
18
19
20
21
22
23
24
FLDO
SYNCST
CS
SCLK
SIN
BUS
Y
XD
EXD
VSS
VCC
PO0
PO1
MB90050
IC428
: M3087BFLBGP
Micr
opr
ocessor
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Port P14
Port P15
Port P11
Port P12
Port P10
Port P9
Port P8
P8
5
Port P13
R0H
R0L
R1H
R1L
R2
R3
A0
A1
FB
SB
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package only.
2. Included in the 144-pin package only.
3. 6 channels available in the 100-pin package.
4. 6 channels available in the 100-pin package.
5. 10 channels available in the 100-pin package.
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
Multiplier
M32C/80 series
micr
opr
ocessor
core
Clock Generation Circuit
X
IN
- X
OUT
X
CIN
- X
COUT
On-chip Oscillator
PLL Frequency Synthesizer
A/D Converter:
1 circuit
Standard: 10 inputs
Maximum: 34 inputs
(2)
(3)
(4)
(5)
UART/Clock Synchronous Serial I/O:
7-channel
CRC Calculation Circuit (CCITT):
X
16
+X
12
+X
5
+1
X/Y Converter:
16-bit x 16-bit
D/A Converter:
8-bit x 2-channel
Peripheral Functions
<
V
CC2
>
<
V
CC1
>
<
V
CC1
>
ROM
RAM
Memory
<
V
CC1
>
<
V
CC2
>
78
5
8
8
(Note 1)
8
8
7
888888
8
8
DMACII
DMAC
Watchdog Timer (15-bit)
Intelligent I/O
Time Measurement: 8-channel
Waveform Generating: 8-channel
Communication Functions:
Clock Synchronous Serial I/O, UART,
HDLC Data Processing
Timer (16-bit)
Timer A: 5-channel
Timer B: 6-channel
Three-Phase Motor Control Circuit
IC BLOCK DIGAGRAM MAIN 3/4
YSP-4100/YSP-5100
YSP-5100
