Yamaha AFC1, Service Manual

Page: 12 / 108

AFC1
12
LSI PIN DESCRIPTION
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
PE14
PE15
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
VCC
A17
VSS
/RAS
/CASL
/CASH
VSS
RDWR / PB5
A18
A19
A20
PB9 /A21
VSS
/RD
/WDTOVF
/WRH
VCC
/WRL
VSS
/CS1
/CS0
PA9 / TCLKD
/IRQ2 / TCLKC
/CS3
/CS2
/IRQ1
TXD
RXD
/IRQ0
PA1 / TXD0
PA0 / RXD0
D15
D14
D13
VSS
D12
O
O
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
I
O
O
O
O
O
O
O
O
O
I
O
O
O
I
O
I
O
O
O
I
O
O
I
O
I
I
O
I
I/O
I/O
I/O
I
I/O
Port E
Port E
Ground
Address bus
Power supply
Address bus
Ground
Row address strobe
Column address strobe (low)
Column address strobe (high)
Ground
DRAM read/write / Port B
Address bus
Port B / Address bus
Ground
Read
Watch dog timer overflow
High write
Power supply
Low write
Ground
Chip select
Chip select
Port A / Timer clock
Interrupt request / Timer clock
Chip select
Chip select
Interrupt request
Data transmission
Data reception
Interrupt request
Port A / Data transmission
Port A / Data reception
Data bus
Ground
Data bus
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
D11
D10
D9
D8
VSS
D7
D6
D5
VCC
D4
D3
D2
D1
D0
VSS
XTAL
MD3
EXTAL
MD2
NMI
VCC
MD1
MD0
PLLVCC
PLLCAP
PLLVSS
PA15 / CK
/RES
PE0
PE1
PE2
PE3
PE4
VSS
AN0 / PF0
AN1 / PF1
AN2 / PF2
AN3 / PF3
AN4 / PF4
AN5 / PF5
AVSS
AN6 / PF6
AN7 / PF7
AVCC
VSS
PE5
VCC
PE6
PE7
PE8
PE9
PE10
VSS
PE11
PE12
PE13
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
O
O
O
O
O
I
O
O
O
Data bus
Ground
Data bus
Power supply
Data bus
Ground
Crystal oscillator
Mode control
Crystal oscillator
Mode control
Non-maskable interrupt request
Power supply
Mode control
Mode control
PLL Power supply
PLL capacitor
PLL Ground
Port A / Clock
Reset
Port E
Ground
Analog input / Port F
Analog ground
Analog input / Port F
Analog input / Port F
Power supply
Ground
Port E
Power supply
Port E
Ground
Port E
HD6437042AF62F (XY885B00) CPU
MAIN: IC004
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EPM7128SQC100-7 (XY976C00) FPGA (Field Programmable Gate Array) .................................... 15
YM3436DK (XG948E00) DIR2 (Digital Format Interface Receiver) .................................................. 16
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（LSI 端子機能表）