AFC1
16
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DAUX
HDLT
DOUT
VFL
OPT
SYNC
MCC
WC
MCB
MCA
SKSY
XI
XO
P256
LOCK
Vss
TC
DIM1
DIM0
DOM1
DOM0
KM1
I
O
O
O
O
O
O
O
O
O
I
I
O
O
O
O
I
I
I
I
I
Auxiliary input for audio data
Asynchronous buffer operation flag
Audio data output
Parity flag output
Fs x 1 Synchronous output signal for DAC
Fs x 1 Synchronous output signal for DSP
Fs x 64 Bit clock output
Fs x 1 Word clock output
Fs x 128 Bit clock output
Fs x 256 Bit clock output
Clock synchronization control input
Crystal oscillator connection or external
clock input
Crystal oscillator connection
VCO oscillating clock connection
PLL lock flag
Logic section power (GND)
PLL time constant switching output
Data input mode selection
Data input mode selection
Data output mode selection
Data output mode selection
Clock mode switching input 1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
RSTN
Vdda
CTLN
PCO
(NC)
CTLP
Vssa
TSTN
KM2
KM0
FS1
FS0
CSM
EXTW
DDIN
LR
Vdd
ERR
EMP
CD0
CCK
CLD
I
I
O
I
I
I
I
O
O
I
I
I
O
O
O
O
I
I
System reset input
VCO section power (+5 V)
VCO control input N
PLL phase comparison output
VCO control input P
VCO section power (GND)
Test terminal. Open for normal use
Clock mode switching input 2
Clock mode switching input 0
Channel status sampling frequency
display output 1
Channel status sampling frequency
display output 0
Channel status output method selection
External synchronous auxiliary input
word clock
EIAJ (AES/EBU) data input
PLL word clock output
Logic section power (+5 V)
Data error flag output
Channel status emphasis control code
output
3-wire type microcomputer interface data
output
3-wire type microcomputer interface clock
input
3-wire type microcomputer interface load
input
YM3436DK (XG948E00) DIR2 (Digital Format Interface Receiver)
PIN
NO.
I/O
FUNCTION
NAME
PIN
NO.
I/O
FUNCTION
NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
/DSRA
/CTSA
/DTRA
VCC
/RTSA
INTA
/CSA
TXA
/LOW
TXB
/CSB
INTB
/RTSB
GND
/DTRB
/CTSB
/DSRB
/CDB
/RIB
RXB
VCC
A2
A1
A0
XTAL1
XTAL2
RESET
GND
RXC
/RIC
/CDC
/DSRC
I
I
O
I
O
O
I
O
I
O
I
O
O
O
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
Data set ready (active low)
Clear to send (active low)
Data terminal ready (active low)
Power supply inputs
Request to send (active low)
Interrupt A (active high)
Chip select
Transmit data
Write strobe
Transmit data
Chip select
Interrupt B (active high)
Request to send (active low)
Signal and power ground
Data terminal ready (active low)
Clear to send (active low)
Data set ready (active low)
Carrier detect (active low)
Ring indicator (active low)
Receive data input RX B
Power supply inputs
Address bus
Crystal or External clock input
Output of the crystal oscillator or buffered clock
Reset
Signal and power ground
Receive data input RX C
Ring indicator (active low)
Carrier detect (active low)
Data set ready (active low)
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
/CTSC
/DTRC
VCC
/RTSC
INTC
/CSC
TXC
/IOR
TXD
/CSD
INTD
/RTSD
GND
/DTRD
/CTSD
/DSRD
/CDD
/RID
RXD
VCC
D0
D1
D2
D3
D4
D5
D6
D7
GND
RXA
/RIA
/CDA
I
O
I
O
O
I
O
I
O
I
O
O
O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
Clear to send (active low)
Data terminal ready (active low)
Power supply inputs
Request to send (active low)
Interrupt C (active high)
Chip select
Transmit data
Read strobe
Transmit data
Chip select
Interrupt D (active high)
Request to send (active low)
Signal and power ground
Data terminal ready (active low)
Clear to send (active low)
Data set ready (active low)
Carrier detect (active low)
Ring indicator (active low)
Receive data input RX D
Power supply inputs
Data bus
Signal and power ground
Receive data input RX A
Ring indicator (active low)
Carrier detect (active low)
ST16C554DCQ64 (XW934A00) UART
(Universal asynchronous receiver and transmitter)
