AHIP-370 Manual
56
Flat Panel Connector (FPNL1 and FPNL2)
Pin
Signal
Pin
Signal
1
GND
31
GND
2
SHFCLK
32
P(4)
3
GND
33
P(5)
4
LP
34
P(6)
5
FLM
35
P(7)
6
GND
36
GND
7
P(16)
37
M
8
P(17)
38
VCCSW
9
P(18)
39
VCCSW
10
P(19)
40
+5V
11
GND
41
+5V
12
P(20)
42
PANEL_LOGIC
13
P(21)
43
PANEL_LOGIC
14
P(22)
44
+3.3V_CPU
15
P(23)
45
+3.3V_CPU
16
GND
46
GND
17
P(8)
47
FPSEL(0)
18
P(9)
48
FPSEL(1)
19
P(10)
49
FPSEL(2)
20
P(11)
50
FPSEL(3)
21
GND
51
+12V
22
P(12)
52
NC(Note 1)
23
P(13)
53
ENAVEE
24
P(14)
54
POT_DQ
25
P(15)
55
POT_CLK
26
GND
56
POT_RST*
27
P(0)
57
TEMP_RST*
28
P(1)
58
ENAVDD
29
P(2)
59
ENABCK
30
P(3)
60
RESET*
Backlight Inverter Connector (DCINV1)
Pin
Signal
1
+12V (switched)
2
+12V (switched)
3
Undefined Voltage
4
ENABKL (thru 10K
Ω
res
5
Undefined Voltage
6
Undefined Voltage
7
GND
8
GND
Summary of Contents for AHIP-370
Page 6: ...AHIP 370 Manual 6 Architecture Figure 1 1 AHIP 370 Block diagram...
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