Xycom AHIP-370, Manual

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AHIP-370 Manual
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Registers
The AHIP-370 contains five I/O ports: 231h, 233h, 234h, and a user-definable port
(port 180/1h, 2E0/1h, 3E0/1h, or 300/1h). These ports are compatible with AHIP4+
and AHIP 6+.
Register 231h – Miscellaneous Control
Register 231h controls the LEDs and signals shown in the following table.
Table 2- 7. Register 231h - CPU LED Port
Bit LED/Signal Result R/W
0 Reserved 0 R
1 DOC 2000 1= Enables DOC 2000 R/W
2 Reserved 0 R
3 Reserved 0 R
4 Reserved 0 R
5* ENFLASHWR 1 = Enables Flash write R/W
6 VGA_EN 1 = Enables on-board VGA R
7 CLRCMS 1 = CMOS okay
0 = Clear CMOS R
*Note: This bit must be 1 to make FLASH visible @D0000h when booting from
AT bus. This bit also enables the FLASH @C0000h when booting to FLASH.
Register 233h – Flash BIOS Control
Register 233h controls the signals shown in the following table.
Table 2- 8. Register 233h - Flash BIOS Control Register
Bit Signal Result R/W
0 FLA15 Flash address 15 - page control bit R/W
1 FLA16 Flash address 16- page control bit R/W
2 FLA17 Flash address 17 - page control bit R/W
3 FLA18 Flash address 18 - page control bit R/W
4 FPSEL0 Flat panel select bit 0 R
5 FPSEL1 Flat panel select bit 1 R
6 FPSEL2 Flat panel select bit 2 R
7 FPSEL3 Flat panel select bit 3 R