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Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 5:
Tile Features
R
Ports and Attributes
defines the shared clocking ports.
defines the shared clocking attributes.
Description
Clocking from an External Source
Each GTP_DUAL tile has a pair of dedicated pins that can be connected to an external
clock source. To use these pins, an IBUFDS primitive is instantiated. In the User
Constraints file, the IBUFDS input pins are constrained to the locations of the dedicated
clock pins for the GTP_DUAL tile. In the design, the output of the IBUFDS is connected to
the CLKIN port. The locations of the dedicated pins for all the GTP_DUAL tiles are
documented in
Chapter 10, “GTP-to-Board Interface”
provides a selection of suitable external oscillators and describes the board-level
requirements for the dedicated reference clock.
shows a differential GTP clock
pin pair sourced by an external oscillator on the board. Refer to
for IBUFDS details.
Table 5-4:
Shared Clocking Ports
Port
Dir
Clock Domain
Description
CLKIN
In
N/A
Reference clock input to the shared PMA PLL.
REFCLKOUT
Out
N/A
The REFCLKOUT port from each GTP_DUAL
tile provides access to the reference clock
provided to the shared PLL (CLKIN). It can be
routed for use in the FPGA logic.
Table 5-5:
Shared Clocking Attributes
Attribute
Description
CLK25_DIVIDER
The internal digital logic for GTP_DUAL tile management runs at about
25 MHz. CLK25_DIVIDER is set to get an internal clock for the tile.
1: CLKIN < 25 MHz
2: 25 MHz < CLKIN < 50 MHz
3: 50 MHz < CLKIN < 75 MHz
4: 75 MHz < CLKIN < 100 MHz
5: 100 MHz < CLKIN < 125 MHz
6: 125 MHz < CLKIN < 150 MHz
10: 150 MHz < CLKIN < 250 MHz
12: CLKIN > 250 MHz
CLKINDC_B
Must be set to TRUE. Oscillators driving the dedicated reference clock
inputs must be AC coupled.
Figure 5-4:
Single GTP_DUAL Tile Clocked Externally
GTP_DUAL
MGTREFCLKP
IBUFDS
MGTREFCLK
N
CLKI
N
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