Virtex-5 RocketIO GTP Transceiver User Guide
67
UG196 (v1.3) May 25, 2007
Shared PMA PLL
R
7.
Select the PLL divider values
Select the smallest divider values that result in the required PLL divider ratio. In this
case, using PLL_DIVSEL_FB = 2 and PLL_DIVSEL_REF = 1 results in a ratio of two.
Configuring Shared PLL for PCI Express
This example shows how to set the shared PLL divider settings for PCI Express using
. The RocketIO GTP Wizard and
are simpler alternatives. This
example is provided only to illustrate the process with
.
Use
as described in the following steps:
1.
Determine the required line rates.
For PCI Express, both TX and RX use a line rate of 2.5 Gb/s.
2.
Determine the internal datapath width.
Because PCI Express uses 8B/10B encoding, an internal datapath width of 10 bits is
required.
3.
Determine the desired reference clock rate.
This example uses a reference clock running at 100 MHz.
4.
Calculate the required PLL clock rate.
Because the SIPO block uses both edges of the clock to deserialize data, it must be fed
a clock running at 2.5/2 = 1.25 GHz. Because this RX rate of 1.25 GHz is within the
operating range of the PLL, the external divider (PLL_RXDIVSEL_OUT) must be one.
The PLL clock rate is thus 1.25 x 1 = 1.25 GHz.
5.
Calculate the required DIV value
Because the internal datapath with must be 10 bits and INTDATAWIDTH = 1, DIV = 5.
6.
Calculate the required PLL divider ratio
Using the values f
CLKIN
, DIV, and f
PLL_CLOCK
determined above, rearrange
to calculate the divider ratio as shown in
. The result is a
ratio of 2.5.
Equation 5-5
7.
Select the PLL divider values
Select the smallest divider values that result in the required PLL divider ratio. In this
case, using PLL_DIVSEL_FB = 5 and PLL_DIVSEL_REF = 2 results in a ratio of 2.5.
PLL
_
DIVSEL
_
FB
PLL
_
DIVSEL
_
REF
-----------------------------------------------------
f
PLL
_
Clock
f
CLKIN
DIV
×
-----------------------------------
1.25
GHz
100
MHz
5
×
----------------------------------
2.5
=
=
=
