Xilinx Virtex-5 RocketIO GTP, User Manual

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92 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 6: GTP Transmitter (TX)
R
Figure 6-2 shows how TXDATA is transmitted serially when the internal datapath is 8 bits
(INTDATAWIDTH =
0
) and 8B/10B encoding is disabled.
Figure 6-3 shows how TXDATA is transmitted serially when the internal datapath is 10 bits
(INTDATAWIDTH =
1
) and 8B/10B encoding is disabled. When TXDATA is 10 bits or
20 bits wide, the TXCHARDISPMODE and TXCHARDISPVAL ports are taken from the
8B/10B encoder interface and used to send the extra bits.
When 8B/10B encoding is used, the data interface is a multiple of 8 bits ( Figure 6-2 ), and
the data is encoded before it is transmitted serially. “Configurable 8B/10B Encoder,” page
98 provides more details about bit ordering when using 8B/10B encoding.
Connecting TXUSRCLK and TXUSRCLK2
The FPGA TX interface includes two parallel clocks: TXUSRCLK and TXUSRCLK2.
TXUSRCLK is the internal clock for the PCS logic in the GTP transmitter. The required rate
for TXUSRCLK depends on the internal datapath width of the GTP_DUAL tile
(INTDATAWIDTH), and the TX line rate of the GTP transmitter (
“Parallel In to Serial Out
(PISO),” page 110 describes how the TX line rate is determined). Equation 6-1 shows how
to calculate the required rate for TXUSRCLK.
Equation 6-1
TXUSRCLK2 is the main synchronization clock for all signals into the TX side of the GTP
transceiver. Most signals into the TX side of the GTP transceiver are sampled on the
1 1 0
20 bits
1 1 1
16 bits
Figure 6-2: 8B/10B Bypassed, 8-Bit Internal Datapath
Table 6-2: TX Datapath Width Configuration (Continued)
INTDATAWIDTH TXDATAWIDTH TXENC8B10BUSE FPGA TX Interface Width
UG196_c6_02_051206
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Transmitted
Last
Transmitted
Last
Transmitted
First
Transmitted
First
TXDATA
TXDATA W IDTH = 0 TXDATA W IDTH = 1
TXDATA
Figure 6-3: 8B/10B Bypassed, 10-Bit Internal Datapath
TXDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
UG196_c6_03_052406
Transmitted
Last
Transmitted
Last
Transmitted
First
Transmitted
First
TXDATA
TXDATA W IDTH = 1 TXDATA W IDTH = 0
TXCHARDISPMODE[1]
TXCHARDIPS V AL[1]
TXCHARDISPMODE[0]
TXCHARDIPS V AL[0]
TXCHARDISPMODE[0]
TXCHARDIPS V AL[0]
TXUSRCLK Rate
Line Rate
Internal Datapath Width
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