Xilinx LogiCORE IP, User Manual

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82 www.xilinx.com Video Scaler v4.0 User Guide
UG805 March 1, 2011
Appendix B: Programmer Guide
Name Bits Description
Reserved 31:4 Reserved
coef_write_set_addr 3:0 Coefficient bank to write, address
Table B-18: coef_values Register
0x0040 coef_values W
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
coef_1 coef_value_N
Name Bits Description
coef_1 31:16
Coefficient value N+1 where N is index for the coefficient
set.
Usage: Each write to this register increments an internal
counter by 2 to generate a coefficient set internal to the
video scaler. LSB aligned for coefficients less than 16 bits.
coef_value_N 15:0
Coefficient value N where N is index for the coefficient
set.
Usage: Each write to this register increments an internal
counter by 2 to generate a coefficient set internal to the
video scaler. LSB aligned for coefficients less than 16 bits
Table B-19: Coefficient Set and Bank Read Address Register
0x0044 coef_set_bank_rd_addr R/W
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
Reserved Set Reserved Bank
Name Bits Description
Coeff Readback Set 11:8 Coefficient set to be read from the scaler
Coeff Readback Bank 1:0
Coefficient bank to be read from scaler:
00=HY; 01=HC; 10=VY; 11=VC
Table B-17: Coefficient_write_set_address Register